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Tue, 28 Jul 2026 23:51:57 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Boris Pismenny , Carolina Jubran , Cosmin Ratiu , Daniel Zahka , Dragos Tatulea , Gal Pressman , "Kees Cook" , Leon Romanovsky , , , Mark Bloch , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Tariq Toukan Subject: [PATCH net] net/mlx5e: Add mutual exclusion between PSP and PTP TX port timestamping Date: Wed, 29 Jul 2026 09:51:37 +0300 Message-ID: <20260729065137.2420679-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C8:EE_|SA3PR12MB8762:EE_ X-MS-Office365-Filtering-Correlation-Id: 586443c5-fe0c-4365-0e3b-08deed3dec45 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|82310400026|376014|23010399003|36860700016|6133799003|11063799006|56012099006|10067099003|18002099003; X-Microsoft-Antispam-Message-Info: ndyV8ws4C5PHs8d76Mk22A1tqcY7hCGc2jKdDuohaZzSvq9OrSkhYEj2ACEXVOpB/067C38edtDHqsNxtz8b0NgBtzlvnSUfNd2BhE8j+Z+wharTsh9eyq5glFRxeqo1Ho4hF6zNHKjAaYHk9Dh5pXDgwkAGb4fqQ+ekbm6JlPRFV0j1ha7wRPeCxqP+JefE9EULXidFFqeJ/4KZMUDT+BHMQqPPykFkD6o/U/815D1NrqfN2JZKyhwoXr/AAaIqTkjKJ/9Awd6TGTQ5GJ95x4X0h9niS/xgd5R3e0dm+RhYrkdMf5y92/T8sF14eXlkjszX0BRdFf5pgnm99dNKJCmVfodFrJcDz5kNlbdXl4JygTzdMPllHLw19dN2XlocWciFzbDB1M8tNTx8NjQO+yHRhwozbpv86Zz5UdR1RCgb08RRRfZzWuugd3DUK7WzC4J/ATavwdGhmvaX81QKAxwXohL4TSkb0LkbVUlQnQDp+Id60hGiJJ0fc0XzyOlX8eI42jtjQWdLVN8ssnyoyaTRMP21OTPaZ8z4sGCZx/oysgC1Hf1XoHifBgK11eHmoRqpFFswwU3AOqrvZ8mwezoCDCxfcppKhTBanAlsYtyjVn/qNaUF1usnQ6iEyDa9gp0fW6MxaDiGExTV3JiIDP58yp9XqFrnh186jJx6L9NC1Qwi0HCDjSc3o/u/d/zw1YWiYEmXI7IcID6is8WzQA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(82310400026)(376014)(23010399003)(36860700016)(6133799003)(11063799006)(56012099006)(10067099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PXCL/0nV0BYIGYlXjoCECvSLjOGbPuUC4rb4n8AxHGO1VGQkAbDFzM43Lzfhhdmf0Dsss3yOEt9csHz11YYsHdEuXFkQYiE7C+99I3yCcXqy75XDNEh1u9oP1yzJHnTipc5OAecRbjMMyd0YZ7oQBSuxbiE92Aw5tyJRI9sNE2kefPzsKDKsrqhH964gYC6ncrjZijttMIBgBxPJ+b1rVWXeqTuPZs0wF5sErady7E0z1ESfIp/R1Zp6ZS8ODpK3HkAkWJ4aLOXR9/te1APjbprYqoyxfyJqGw3z4TjEvPJ18/OgudhxQlv2UBYqWWARA4pWXYfh7uwLn8jvS1wc6iQEEfrBzQZ9M9QrMiei7JGm89Rkto4TrtK1c+SX40v6vrQHaj3J7ff5kj4Zb+pEsAvEPx1UBZCQ3sYQuFXIOa4g8KfMouYqozT5qXBf+qSC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2026 06:52:14.4539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 586443c5-fe0c-4365-0e3b-08deed3dec45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8762 From: Carolina Jubran The WQE flow_table_metadata field is shared by multiple TX offloads: IPsec, MACsec, PTP timestamping and PSP each write to it. Commit [1] resolved the conflicts between IPsec/MACsec and PTP by shifting their markers to bits [8+], leaving PTP's 8-bit metadata index in bits [7:0] without overlap. But then PSP support was added in commit [2], which writes a 32-bit keyid across all bits of flow_table_metadata. Unlike IPsec and MACsec, PTP timestamping applies independently of encryption -- a PSP-encrypted packet can also require a HW timestamp. When both write to the same WQE, the values corrupt each other, leading to wrong PTP timestamp tracking and potentially wrong PSP encryption keys. Prevent the conflict at configuration time by blocking: - Enabling TX-port-TS when PSP has active TX keys. - Adding PSP TX keys when TX-port-TS is already enabled. [1] Commit 2ac207381c37 ("net/mlx5e: Prevent WQE metadata conflicts between timestamping and offloads") [2] Commit 89ee2d92f66c ("net/mlx5e: Support PSP offload functionality") Fixes: 89ee2d92f66c ("net/mlx5e: Support PSP offload functionality") Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_accel/psp.c | 16 +++++++++++++++- .../ethernet/mellanox/mlx5/core/en_accel/psp.h | 11 +++++++++++ .../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 8 ++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index d9adb993e64d..8d76dd488d77 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -993,6 +993,20 @@ static int mlx5e_psp_assoc_add(struct psp_dev *psd, struct psp_assoc *pas, struct psp_key *nkey; int err; + /* Mutual exclusion with TX-port-TS (shared WQE metadata). Reserve + * tx_key_cnt under state_lock with the TS check so ethtool cannot + * enable TX-port-TS until key creation completes or fails. + */ + mutex_lock(&priv->state_lock); + if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) { + mutex_unlock(&priv->state_lock); + NL_SET_ERR_MSG_MOD(extack, + "TX-port-TS is active, PSP TX keys cannot be added"); + return -EBUSY; + } + atomic_inc(&psp->tx_key_cnt); + mutex_unlock(&priv->state_lock); + mdev = priv->mdev; nkey = (struct psp_key *)pas->drv_data; @@ -1001,11 +1015,11 @@ static int mlx5e_psp_assoc_add(struct psp_dev *psd, struct psp_assoc *pas, MLX5_ACCEL_OBJ_PSP_KEY, &nkey->id); if (err) { + atomic_dec(&psp->tx_key_cnt); mlx5_core_err(mdev, "Failed to create encryption key (err = %d)\n", err); return err; } - atomic_inc(&psp->tx_key_cnt); return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h index 6b62fef0d9a7..315c4b2101c2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h @@ -30,6 +30,11 @@ struct mlx5e_psp { atomic_t tx_drop; }; +static inline bool mlx5e_psp_tx_keys_active(const struct mlx5e_priv *priv) +{ + return priv->psp && atomic_read(&priv->psp->tx_key_cnt); +} + static inline bool mlx5_is_psp_device(struct mlx5_core_dev *mdev) { if (!MLX5_CAP_GEN(mdev, psp)) @@ -52,6 +57,11 @@ void mlx5e_psp_unregister(struct mlx5e_priv *priv); int mlx5e_psp_init(struct mlx5e_priv *priv); void mlx5e_psp_cleanup(struct mlx5e_priv *priv); #else +static inline bool mlx5e_psp_tx_keys_active(const struct mlx5e_priv *priv) +{ + return false; +} + static inline int mlx5_accel_psp_fs_init_rx_tables(struct mlx5e_priv *priv) { return 0; @@ -74,4 +84,5 @@ static inline void mlx5e_psp_unregister(struct mlx5e_priv *priv) { } static inline int mlx5e_psp_init(struct mlx5e_priv *priv) { return 0; } static inline void mlx5e_psp_cleanup(struct mlx5e_priv *priv) { } #endif /* CONFIG_MLX5_EN_PSP */ + #endif /* __MLX5E_ACCEL_PSP_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 112926d07634..98941088d100 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -42,6 +42,7 @@ #include "en/ptp.h" #include "lib/clock.h" #include "en/fs_ethtool.h" +#include "en_accel/psp.h" #define LANES_UNKNOWN 0 @@ -2387,6 +2388,13 @@ static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) __func__); return -EINVAL; } + + if (enable && mlx5e_psp_tx_keys_active(priv)) { + netdev_err(priv->netdev, + "%s: PSP TX keys are active, TX-port-TS cannot be enabled\n", + __func__); + return -EBUSY; + } MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable); /* No need to verify SQ stop room as * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both base-commit: 3bd438a58e910db5dc369aa25dfed1fc95f1b596 -- 2.44.0