From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AEC643B3F6; Sat, 1 Aug 2026 11:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785583296; cv=none; b=W+oCxpSY46ys50CVdA3TR0f/Q1UlSzxOiLdjenDJZaI8K6bWiA0QYttS12+wuHZZblwH0JhAAlY1+ASwS++O+cvsN6hGB0VNy9sjxxkruLsLci9xahc1cXvqoWHYHKfu7CA9DvCaRGGEOM3K5BucKU+WDXmxh+3r5/UBth+x6Rc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785583296; c=relaxed/simple; bh=n9wUOpobDjDzuRSQD9VUQ/Ag4R9g26eowejTg9uByGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FO7kOZuxJt/mGIJma1xEUdkGFT6pGmWN9JNvPaRf5ONUf3aLCCQtwqDqCql4HWxHMcd9YK6/DIusG8HZk8V77aETzvCT79Swk56OmT/Y36zOfYpHmEu0FJCSNfYMsXykiu24hl1qDlmPU5016vLQwtpwAc8lhABsn4TOEE+wxcI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lQ35vELX; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lQ35vELX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1785583289; bh=n9wUOpobDjDzuRSQD9VUQ/Ag4R9g26eowejTg9uByGA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lQ35vELXEkZod5kp8HXm5BuHv+QxPaTctnFQXG8WY6wcbynMQUQ+1TbIzR1auvnSL QLSNITIjL2+5rSHLd7Ns2HeNh4OeYBp7G0FfigDjrfor1zQOg7ukKIzaz+BDCnb1qy ZIeGZGug/EbjFXRGvg18tKCKCsnek91pecpYnUZ4YVmCwjPYiiKANSRcVYqxHlSAcT PhMHCl+yghOcCjqYstPTIFq8DeD3qmASLQLP4E8A3XujhkKMMA7mWFNNkUF6QSoP6L AcHTYqsXZzw0hjZsmfWdMJsStCfA3Xa7MOCv39OzUjieqmaX5X6WNf66/JEsaZsWln Rw2q5nx9M8GdA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8E19C17E092F; Sat, 01 Aug 2026 13:21:28 +0200 (CEST) From: Louis-Alexis Eyraud Date: Sat, 01 Aug 2026 13:21:08 +0200 Subject: [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc clock support Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260801-mt8189-clocks-system-base-v5-22-ac4410697cc2@collabora.com> References: <20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com> In-Reply-To: <20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com> To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785583261; l=4468; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=n9wUOpobDjDzuRSQD9VUQ/Ag4R9g26eowejTg9uByGA=; b=eO6vA4sKV+c6KgXZEC8ViERfr03K22X00pwwk8H2X8Ivv68Z0dfcug5JorCpGEv8Ag4G9ZTsK S1r7WuDU80JBksEfeZRAS12zbg/Azp842kqh9LX+IaQKICAxOG/AqT9 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 dvfsrc clock controller, which provides clock gate control for dram dvfs. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/clk/mediatek/Kconfig | 10 ++++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 58 ++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 635b0109ec07..245d3b83b5d3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -849,6 +849,16 @@ config COMMON_CLK_MT8189_DBGAO vcore debug system clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. +config COMMON_CLK_MT8189_DVFSRC + tristate "Clock driver for MediaTek MT8189 dvfsrc" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the dvfsrc + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore dvfs clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 6ab6df7ebf2a..4dbfc9ac83ba 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o +obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c new file mode 100644 index 000000000000..37b81dc0b882 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs dvfsrc_top_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, _flags) + +static const struct mtk_gate dvfsrc_top_clks[] = { + GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en", + "clk26m", 0, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc dvfsrc_top_mcd = { + .clks = dvfsrc_top_clks, + .num_clks = ARRAY_SIZE(dvfsrc_top_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dvfsrc[] = { + { .compatible = "mediatek,mt8189-dvfsrc-top", .data = &dvfsrc_top_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc); + +static struct platform_driver clk_mt8189_dvfsrc_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-dvfsrc", + .of_match_table = of_match_clk_mt8189_dvfsrc, + }, +}; +module_platform_driver(clk_mt8189_dvfsrc_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver"); +MODULE_LICENSE("GPL"); -- 2.55.0