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chris.packham@alliedtelesis.co.nz, daniel@makrotopia.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH net-next v11 03/10] net: mdio: realtek-rtl9300: Add polling documentation Date: Sun, 2 Aug 2026 10:35:21 +0200 Message-ID: <20260802083528.490216-4-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260802083528.490216-1-markus.stockhausen@gmx.de> References: <20260802083528.490216-1-markus.stockhausen@gmx.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:sSwLxJRtioLIZVvUcRifZKO+wQ1UpWcoCbze+5BbX3uK3c1F4RD 64r4lr/wdcnygxrEEkUx4X/SseJQkh4WyhI8BukTtP/sfe0dP9BXlZyhpQ1uRAccu4s6dgQ Cy54ITryIf0IxUCZKP7R+5dcvUKZWPVlDSp/mkf5bqFc9LTdnNhU0TcCKRhT+AfMJJXRR03 dOL9Yu+Oz1k/ZDQcy+ZnQ== X-Spam-Flag: NO UI-OutboundReport: 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dh+3r/iHdQVnBp+rrSH7TWj79pNTQlX+kO5UOu36WOrjHr9TA8uGGGw+jaEqZni8/dbJcI8GE PICr3yOtiqy4d4F6NpxyLykMI7ptRObLzQax1oMlwDFnIA5fE4tX1AA5+QWqor+2CgnfsoZ1i XK/aGC2EJYDeJ//10Y3GT461Uev6XwO5IniVxB5mXInsK9Ppal36ptUXMqwjW3AHdrmqE5Tkk 16Bh7H/BMKv8Kobx01DozN09I/qVfKJoJr1xW1lYt1O2ZYBk8YukbjBZ9ihbYolFnECVBemM9 UBZnc3IOTRJJwjrGHSYvSKla5UxkIRDV/s4+tZG9Q7dbe8WxEhLPR/pEBbkQOsgV3+3GYqmGA txrxVkP8C41om/YppP+sxs1TA== Add a detailed explanation how the hardware polling unit in the Realtek Otto switches works. This simplifies developing future patches and reviewing them. Signed-off-by: Markus Stockhausen =2D-- drivers/net/mdio/mdio-realtek-rtl9300.c | 75 +++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/md= io-realtek-rtl9300.c index afd52a1cd7f8..73ac5fdcd267 100644 =2D-- a/drivers/net/mdio/mdio-realtek-rtl9300.c +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -35,6 +35,81 @@ * * The driver works out the mapping based on the MDIO bus described in de= vice tree and phandles on * the ethernet-ports property. + * + * The devices have a hardware polling unit that runs in the background w= ithout any CPU load. It + * constantly scans the MDIO bus and the attached PHYs and updates the MA= C status registers. + * + * How does the polling work? + * + * Each device has a SMI_POLL_CTRL register. A per-port bitmask decides i= f the hardware polling of + * the associated bus/address is active or not. The hardware runs a tight= loop over this and for + * each set polling bit it issues a status check for the PHY. Attaching a= logic analyzer to the + * MDIO bus of an RTL8380 and RTL8393 gives the following commands (in ke= rnel notation): + * + * RTL8380 RTL8393 + * --------------------------- --------------------------- + * phy_write(phy, 31, 0x0); phy_read(phy, 0); + * phy_write(phy, 13, 0x7); phy_read(phy, 1); + * phy_write(phy, 14, 0x3c); phy_read(phy, 4); + * phy_write(phy, 13, 0x8007); phy_read(phy, 5); + * phy_read(phy, 14); phy_read(phy, 6); + * phy_write(phy, 13, 0x7); phy_read(phy, 9); + * phy_write(phy, 14, 0x3d); phy_read(phy, 10); + * phy_write(phy, 13, 0x8007); phy_read(phy, 15); + * phy_read(phy, 14); phy_write(phy, 13, 0x7); + * phy_read(phy, 9); phy_write(phy, 14, 0x3c); + * phy_read(phy, 10); phy_write(phy, 13, 0x4007); + * phy_read(phy, 15); phy_read(phy, 14); + * phy_read(phy, 0); phy_write(phy, 13, 0x7); + * phy_read(phy, 1); phy_write(phy, 14, 0x3d); + * phy_read(phy, 4); phy_write(phy, 13, 0x4007); + * phy_read(phy, 5); phy_read(phy, 14); + * phy_read(phy, 6); + * + * After one PHY status is read, the polling engine goes over to the next= PHY. If one bus is fully + * scanned it switches over to the next bus. Basically the polling system= is always busy and the + * MAC state is updated in real-time. + * + * This is a glimpse look at the complexity of the polling and leaves out= the C45 case and the MAC + * register update logic afterwards. Important to note: + * + * - 100 MBit downshifts (broken cables) are identified and propagated to= the MAC correctly + * - Access to MDIO_AN_EEE_ADV and MDIO_AN_EEE_LPABLE works via C45 over = C22. + * - It is unclear if these sequences change for different PHYs. + * - Access to Realtek reserved register 26 (link speed) has not yet been= seen. + * + * How does MDIO access from kernel work? + * + * When issuing MDIO accesses via an MMIO based interface the final write= to the command register + * sets a "run command now" bit. Between two polling sequences for differ= ent PHYs the hardware + * checks if a user command needs to run and sends it onto the bus. After= wards it simply continues + * its polling work. Inspecting the command sequence for a paged write on= the logic analyzer gives: + * + * RTL8380 RTL8393 + * --------------------------- --------------------------- + * phy_write(phy, 31, page); phy_write(phy, 31, page); + * phy_write(phy, reg, value); phy_write(phy, reg, value); + * phy_write(phy, 31, 0); + * + * What does this mean? + * + * There are slight differences in polling and PHY access between the mod= els but the challenge + * stays the same. On the one hand that greatly simplifies the MAC layer,= on the other hand it + * has some implications for the kernel PHY subsystem. + * + * - Without the polling and a proper MAC status, some of the link handli= ng features do not work. + * Especially an unpopulated MAC_LINK_STS register cancels operations t= o other MAC registers. + * - The Realtek page register 31 is magically modified in the background= so that polling will + * read the right data. On the RTL838x polling simply resets it to zero= . Other devices seem + * to track the page access "magically" in the background. + * - A C45 over C22 kernel access sequence is most likely to fail because= chances are high that + * the polling engine overwrites registers 13/14 in between. + * - PHY firmware loading can have issues. Especially if a PHY is designe= d to expect a clean + * sequence of registers and values without deviation. + * - An access to one PHY will need to wait for the next free slot of the= polling engine. + * + * Conclusion: The Realtek MDIO bus driver PHY access must know and handl= e any interference that + * arises from the above described hardware polling. */ =20 #include =2D-=20 2.55.0