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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF000055DA.mail.protection.outlook.com (10.167.245.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.0 via Frontend Transport; Wed, 5 Aug 2026 04:42:10 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 4 Aug 2026 23:42:08 -0500 Received: from xhdvineethc40.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Tue, 4 Aug 2026 23:42:05 -0500 From: Vineeth Karumanchi To: , , , , , , CC: , , , Subject: [PATCH net v2] net: macb: configure ENST registers for all queues Date: Wed, 5 Aug 2026 10:12:04 +0530 Message-ID: <20260805044204.272989-1-vineeth.karumanchi@amd.com> X-Mailer: git-send-email 2.44.4 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DA:EE_|IA5PR12MB999277:EE_ X-MS-Office365-Filtering-Correlation-Id: 9eca46c9-a1bf-4552-9ef2-08def2abe9a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|23010399003|18002099003|11063799006|3023799007|13003099007|6133799003|10067099003|56012099006; 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This produced an inconsistent hardware setup that affected the scheduling of the configured queues. This was observed on a GEM instance with four hardware queues, all enabled: Initial configuration: - All four queues are enabled. - enst_on_time_qX registers are left at their reset value (0x0001FFFF). - Only q0 and q1 are configured with valid, non-overlapping ENST schedules (T0 and T1 respectively). - Traffic streams p0 and p1 are bound to q0 and q1. - ENST is enabled only on q0 and q1. Observed behavior: - During T0 on-time, both p0 and p1 packets are transmitted. - During T1 on-time, both p0 and p1 packets are transmitted. With the unused queues (q2 and q3) explicitly programmed with enst_on_time = 0x0: - During T0 on-time, only p0 packets are transmitted. - During T1 on-time, only p1 packets are transmitted. Leaving the ENST on-time registers of unused queues at their reset value (0x0001FFFF) disrupts the scheduling of the configured queues, whereas programming them with 0x0 yields the expected ENST operation. Program the ENST registers for every queue unconditionally. The per-queue configuration array is now allocated for bp->num_queues and indexed directly by queue_id; unconfigured queues are left zero-initialized by kcalloc(), so their registers are cleared. Indexing the array by queue_id also makes the queue_id field in struct macb_queue_enst_config redundant, so drop it. Fixes: 89934dbf169e ("net: macb: Add TAPRIO traffic scheduling support") Signed-off-by: Vineeth Karumanchi --- Changes in v2: - Split the patches for net and net-next. - Updated commit message - Link to v1 : https://lore.kernel.org/netdev/20260724043257.2221030-1-vineeth.karumanchi@amd.com/ --- drivers/net/ethernet/cadence/macb.h | 2 -- drivers/net/ethernet/cadence/macb_main.c | 20 +++++++++----------- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 2de56017ee0d..0ee857c985fa 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -1496,7 +1496,6 @@ struct macb_platform_data { * @start_time_mask: Bitmask representing the start time for the queue * @on_time_bytes: "on" time nsec expressed in bytes * @off_time_bytes: "off" time nsec expressed in bytes - * @queue_id: Identifier for the queue * * This structure holds the configuration parameters for an ENST queue, * used to control time-based transmission scheduling in the MACB driver. @@ -1505,7 +1504,6 @@ struct macb_queue_enst_config { u32 start_time_mask; u32 on_time_bytes; u32 off_time_bytes; - u8 queue_id; }; #endif /* _MACB_H */ diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index d394f1f43b68..d58430fe9c41 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4329,7 +4329,7 @@ static int macb_taprio_setup_replace(struct net_device *ndev, struct macb_queue *queue; u32 queue_mask; u8 queue_id; - size_t i; + size_t i, q; int err; if (conf->num_entries > bp->num_queues) { @@ -4357,7 +4357,7 @@ static int macb_taprio_setup_replace(struct net_device *ndev, return -EINVAL; } - enst_queue = kcalloc(conf->num_entries, sizeof(*enst_queue), GFP_KERNEL); + enst_queue = kcalloc(bp->num_queues, sizeof(*enst_queue), GFP_KERNEL); if (unlikely(!enst_queue)) return -ENOMEM; @@ -4416,13 +4416,12 @@ static int macb_taprio_setup_replace(struct net_device *ndev, goto cleanup; } - enst_queue[i].queue_id = queue_id; - enst_queue[i].start_time_mask = + enst_queue[queue_id].start_time_mask = (start_time_sec << GEM_START_TIME_SEC_OFFSET) | start_time_nsec; - enst_queue[i].on_time_bytes = + enst_queue[queue_id].on_time_bytes = enst_ns_to_hw_units(entry->interval, speed); - enst_queue[i].off_time_bytes = + enst_queue[queue_id].off_time_bytes = enst_ns_to_hw_units(conf->cycle_time - entry->interval, speed); configured_queues |= entry->gate_mask; @@ -4448,15 +4447,14 @@ static int macb_taprio_setup_replace(struct net_device *ndev, gem_writel(bp, ENST_CONTROL, queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); - for (i = 0; i < conf->num_entries; i++) { - queue = &bp->queues[enst_queue[i].queue_id]; + for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { /* Configure queue timing registers */ queue_writel(queue, ENST_START_TIME, - enst_queue[i].start_time_mask); + enst_queue[q].start_time_mask); queue_writel(queue, ENST_ON_TIME, - enst_queue[i].on_time_bytes); + enst_queue[q].on_time_bytes); queue_writel(queue, ENST_OFF_TIME, - enst_queue[i].off_time_bytes); + enst_queue[q].off_time_bytes); } /* Enable ENST for all configured queues in one write */ -- 2.44.4