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[144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-39085ee6b3dsm6210477a91.4.2026.08.09.22.14.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 09 Aug 2026 22:14:53 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-51c0199faafso18257021cf.3 for ; Sun, 09 Aug 2026 22:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1786338891; x=1786943691; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=t4QKjYaMbZqOAs0cJZ9/p42hoFJib08aRaFu+6L5UH4=; b=PjxhbYAKvx6X81I6AfRndNZZNlO/i+5AITQnSSXaFqKiC4OwYVCrzmQoM+VLC90stI wixRHblY+vfiju1ovlYEd0uG74d72k3XoP5akrWRZduow6zq1huwDyVJTuSFW8zDF/wh vnJ1gRyWnb2TLo7gWGOOCcoKssMNt8MkuZvyI= X-Received: by 2002:ac8:5e14:0:b0:517:92a6:fcd5 with SMTP id d75a77b69052e-52ce5fc2b03mr407486481cf.18.1786338891469; Sun, 09 Aug 2026 22:14:51 -0700 (PDT) X-Received: by 2002:ac8:5e14:0:b0:517:92a6:fcd5 with SMTP id d75a77b69052e-52ce5fc2b03mr407486161cf.18.1786338890909; Sun, 09 Aug 2026 22:14:50 -0700 (PDT) Received: from lvnvda3289.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-52d165f2c76sm64862701cf.24.2026.08.09.22.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 22:14:49 -0700 (PDT) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, pavan.chebbi@broadcom.com, andrew.gospodarek@broadcom.com, Ajit Khaparde Subject: [PATCH net-next v6 05/15] bnxt_en: Allocate and free MPC software structures Date: Sun, 9 Aug 2026 22:13:48 -0700 Message-ID: <20260810051358.1244418-6-michael.chan@broadcom.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260810051358.1244418-1-michael.chan@broadcom.com> References: <20260810051358.1244418-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Each MPC consists of a special TX ring and a completion ring. Use existing structs bnxt_tx_ring_info and bnxt_cp_ring_info as control structures. The 2 MPC channels to TCE and RCE that share the MSIX will use a shared completion ring. Reviewed-by: Ajit Khaparde Reviewed-by: Pavan Chebbi Signed-off-by: Michael Chan --- v5: https://lore.kernel.org/netdev/20260710042400.3996847-6-michael.chan@broadcom.com/ Check for P5_PLUS before allocating mpc_info to more clearly document that MPC rings are only supported on P5_PLUS chips. --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 35 ++- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 12 +- drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.c | 208 ++++++++++++++++++ drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.h | 46 ++++ 4 files changed, 294 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index c50be51139a3..d11676d97fed 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -3685,7 +3685,7 @@ static size_t __bnxt_copy_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem, return total_len; } -static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) +void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) { struct pci_dev *pdev = bp->pdev; int i; @@ -3718,7 +3718,7 @@ static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) } } -static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) +int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) { struct pci_dev *pdev = bp->pdev; u64 valid_bit = 0; @@ -4325,6 +4325,8 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp) (!sh && i >= bp->rx_nr_rings)) { cp_count += tcs; tx = 1; + if (bnxt_napi_has_mpc(bp, i)) + cp_count++; } cpr->cp_ring_arr = kzalloc_objs(*cpr, cp_count); @@ -4346,6 +4348,11 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp) } else { int n, tc = k - rx; + /* MPC rings are at the highest k indices */ + if (tc >= tcs) { + bnxt_set_mpc_cp_ring(bp, i, cpr2); + continue; + } n = BNXT_TC_TO_RING_BASE(bp, tc) + j; bp->tx_ring[n].tx_cpr = cpr2; cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_TX; @@ -4478,6 +4485,7 @@ static void bnxt_init_ring_struct(struct bnxt *bp) rmem->vmem = (void **)&txr->tx_buf_ring; } } + bnxt_init_mpc_ring_struct(bp); } static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) @@ -5557,6 +5565,7 @@ static void bnxt_init_l2_fltr_tbl(struct bnxt *bp) static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) { bnxt_free_vnic_attributes(bp); + bnxt_free_mpc_rings(bp); bnxt_free_tx_rings(bp); bnxt_free_rx_rings(bp); bnxt_free_cp_rings(bp); @@ -5570,6 +5579,7 @@ static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) bnxt_free_port_stats(bp); bnxt_free_ring_grps(bp); bnxt_free_vnics(bp); + bnxt_free_mpcs(bp); kfree(bp->tx_ring_map); bp->tx_ring_map = NULL; kfree(bp->tx_ring); @@ -5679,6 +5689,10 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) txr->tx_cpr = &bnapi2->cp_ring; } + rc = bnxt_alloc_mpcs(bp); + if (rc) + goto alloc_mem_err; + rc = bnxt_alloc_stats(bp); if (rc) goto alloc_mem_err; @@ -5707,6 +5721,10 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) if (rc) goto alloc_mem_err; + rc = bnxt_alloc_mpc_rings(bp); + if (rc) + goto alloc_mem_err; + rc = bnxt_alloc_cp_rings(bp); if (rc) goto alloc_mem_err; @@ -7268,10 +7286,15 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); req->length = cpu_to_le32(bp->tx_ring_mask + 1); req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); - req->queue_id = cpu_to_le16(ring->queue_id); - if (bp->flags & BNXT_FLAG_TX_COAL_CMPL) - req->cmpl_coal_cnt = - RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64; + if (ring->queue_id == BNXT_MPC_QUEUE_ID) { + req->mpc_chnls_type = ring->mpc_chnl_type; + req->enables |= cpu_to_le32(RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE); + } else { + req->queue_id = cpu_to_le16(ring->queue_id); + if (bp->flags & BNXT_FLAG_TX_COAL_CMPL) + req->cmpl_coal_cnt = + RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64; + } if ((bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP) && bp->ptp_cfg) flags |= RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE; req->flags = cpu_to_le16(flags); diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index 7d3311f10ad5..bd6befe6d29d 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -686,6 +686,7 @@ struct nqe_cn { #define BNXT_NQ_HDL_TYPE_SHIFT 24 #define BNXT_NQ_HDL_TYPE_RX 0x00 #define BNXT_NQ_HDL_TYPE_TX 0x01 +#define BNXT_NQ_HDL_TYPE_MP 0x02 #define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK) #define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \ @@ -951,6 +952,8 @@ struct bnxt_ring_struct { }; u32 handle; u8 queue_id; +#define BNXT_MPC_QUEUE_ID 0xff + u8 mpc_chnl_type; }; struct tx_push_bd { @@ -991,12 +994,16 @@ struct bnxt_tx_ring_info { u16 tx_cons; u16 tx_hw_cons; u16 txq_index; + /* index for tx_ring[] or tx_mpc_ring[] in struct bnxt_napi */ u8 tx_napi_idx; u8 kick_pending; struct bnxt_db_info tx_db; struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; - struct bnxt_sw_tx_bd *tx_buf_ring; + union { + struct bnxt_sw_tx_bd *tx_buf_ring; + struct bnxt_sw_mpc_tx_bd *tx_mpc_buf_ring; + }; dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; @@ -1242,6 +1249,7 @@ struct bnxt_napi { struct bnxt_cp_ring_info cp_ring; struct bnxt_rx_ring_info *rx_ring; struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI]; + struct bnxt_tx_ring_info **tx_mpc_ring; void (*tx_int)(struct bnxt *, struct bnxt_napi *, int budget); @@ -2965,6 +2973,8 @@ int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx); bool bnxt_bs_trace_avail(struct bnxt *bp, u16 type); +void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem); +int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem); void bnxt_set_tpa_flags(struct bnxt *bp); void bnxt_set_ring_params(struct bnxt *); void bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.c index 26eef764c544..a595c9b36218 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.c @@ -12,6 +12,9 @@ void bnxt_alloc_mpc_info(struct bnxt *bp, u8 mpc_chnls_cap) { + if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS)) + return; + if (!bp->mpc_info) bp->mpc_info = kzalloc_obj(*bp->mpc_info); if (bp->mpc_info) @@ -22,6 +25,8 @@ void bnxt_alloc_mpc_info(struct bnxt *bp, u8 mpc_chnls_cap) void bnxt_free_mpc_info(struct bnxt *bp) { + bnxt_free_mpc_rings(bp); + bnxt_free_mpcs(bp); kfree(bp->mpc_info); bp->mpc_info = NULL; } @@ -47,6 +52,55 @@ int bnxt_mpc_cp_rings_in_use(struct bnxt *bp) return mpc->mpc_cp_rings; } +bool bnxt_napi_has_mpc(struct bnxt *bp, int i) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + struct bnxt_napi *bnapi = bp->bnapi[i]; + struct bnxt_tx_ring_info *txr; + + if (!mpc) + return false; + + txr = bnapi->tx_ring[0]; + if (txr && !(bnapi->flags & BNXT_NAPI_FLAG_XDP)) + return txr->txq_index < mpc->mpc_cp_rings; + return false; +} + +void bnxt_set_mpc_cp_ring(struct bnxt *bp, int bnapi_idx, + struct bnxt_cp_ring_info *cpr) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + struct bnxt_napi *bnapi; + bool found = false; + int i, j; + + if (!mpc) + return; + bnapi = bp->bnapi[bnapi_idx]; + /* Check both TCE and RCE MPCs for the matching NAPI */ + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + int num = mpc->mpc_ring_count[i]; + + for (j = 0; j < num; j++) { + struct bnxt_tx_ring_info *txr = &mpc->mpc_rings[i][j]; + + /* Only 1 ring with index j will use this NAPI */ + if (txr->bnapi == bnapi) { + txr->tx_cpr = cpr; + txr->tx_napi_idx = i; + bnapi->tx_mpc_ring[i] = txr; + found = true; + break; + } + } + } + if (!found) + netdev_warn_once(bp->dev, "No MPC match for napi index %d\n", + bnapi_idx); + cpr->cp_ring_type = BNXT_NQ_HDL_TYPE_MP; +} + void bnxt_trim_mpc_rings(struct bnxt *bp) { struct bnxt_mpc_info *mpc = bp->mpc_info; @@ -117,3 +171,157 @@ void bnxt_set_dflt_mpc_rings(struct bnxt *bp) mpc->mpc_ring_count[i] = per_type; mpc->mpc_cp_rings = mpc_cp; } + +void bnxt_init_mpc_ring_struct(struct bnxt *bp) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + int i, j; + + if (!BNXT_MPC_CRYPTO_CAPABLE(bp)) + return; + + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + int num = mpc->mpc_ring_count[i]; + + if (!mpc->mpc_rings[i]) + continue; + for (j = 0; j < num; j++) { + struct bnxt_ring_mem_info *rmem; + struct bnxt_ring_struct *ring; + struct bnxt_tx_ring_info *txr; + + txr = &mpc->mpc_rings[i][j]; + + txr->tx_ring_struct.ring_mem.flags = + BNXT_RMEM_RING_PTE_FLAG; + txr->bnapi = bp->tx_ring[bp->tx_ring_map[j]].bnapi; + txr->txq_index = j; + + ring = &txr->tx_ring_struct; + rmem = &ring->ring_mem; + rmem->nr_pages = bp->tx_nr_pages; + rmem->page_size = HW_TXBD_RING_SIZE; + rmem->pg_arr = (void **)txr->tx_desc_ring; + rmem->dma_arr = txr->tx_desc_mapping; + rmem->vmem_size = SW_MPC_TXBD_RING_SIZE * + bp->tx_nr_pages; + rmem->vmem = (void **)&txr->tx_mpc_buf_ring; + } + } +} + +int bnxt_alloc_mpcs(struct bnxt *bp) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + int i, rc = 0; + + if (!BNXT_MPC_CRYPTO_CAPABLE(bp)) + return 0; + + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + int num = mpc->mpc_ring_count[i]; + struct bnxt_tx_ring_info *txr; + + if (!num) + continue; + txr = kzalloc_objs(*txr, num); + if (!txr) { + rc = -ENOMEM; + goto alloc_mpcs_exit; + } + mpc->mpc_rings[i] = txr; + } + + for (i = 0; i < bp->cp_nr_rings; i++) { + struct bnxt_napi *bnapi = bp->bnapi[i]; + + if (!bnxt_napi_has_mpc(bp, i)) + continue; + bnapi->tx_mpc_ring = kzalloc_objs(*bnapi->tx_mpc_ring, + BNXT_MPC_TYPE_MAX); + if (!bnapi->tx_mpc_ring) { + rc = -ENOMEM; + goto alloc_mpcs_exit; + } + } +alloc_mpcs_exit: + if (rc) + bnxt_free_mpcs(bp); + return rc; +} + +void bnxt_free_mpcs(struct bnxt *bp) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + int i; + + if (!mpc) + return; + + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + kfree(mpc->mpc_rings[i]); + mpc->mpc_rings[i] = NULL; + } + if (!bp->bnapi) + return; + for (i = 0; i < bp->cp_nr_rings; i++) { + struct bnxt_napi *bnapi = bp->bnapi[i]; + + kfree(bnapi->tx_mpc_ring); + bnapi->tx_mpc_ring = NULL; + } +} + +int bnxt_alloc_mpc_rings(struct bnxt *bp) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + int i, j, rc = 0; + + if (!mpc) + return 0; + + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + int num = mpc->mpc_ring_count[i]; + + for (j = 0; j < num; j++) { + struct bnxt_tx_ring_info *txr = &mpc->mpc_rings[i][j]; + struct bnxt_ring_struct *ring; + + ring = &txr->tx_ring_struct; + rc = bnxt_alloc_ring(bp, &ring->ring_mem); + if (rc) + goto alloc_mpc_rings_exit; + ring->queue_id = BNXT_MPC_QUEUE_ID; + ring->mpc_chnl_type = i; + /* for stats context */ + ring->grp_idx = txr->bnapi->index; + spin_lock_init(&txr->tx_lock); + } + } +alloc_mpc_rings_exit: + if (rc) + bnxt_free_mpc_rings(bp); + return rc; +} + +void bnxt_free_mpc_rings(struct bnxt *bp) +{ + struct bnxt_mpc_info *mpc = bp->mpc_info; + int i, j; + + if (!mpc) + return; + + for (i = 0; i < BNXT_MPC_TYPE_MAX; i++) { + int num = mpc->mpc_ring_count[i]; + + if (!mpc->mpc_rings[i]) + continue; + for (j = 0; j < num; j++) { + struct bnxt_tx_ring_info *txr = &mpc->mpc_rings[i][j]; + struct bnxt_ring_struct *ring = &txr->tx_ring_struct; + + bnxt_free_ring(bp, &ring->ring_mem); + } + } +} diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.h index 6d50ca8c45ab..90aec8e0955a 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_mpc.h @@ -29,6 +29,12 @@ struct bnxt_mpc_info { struct bnxt_tx_ring_info *mpc_rings[BNXT_MPC_TYPE_MAX]; }; +struct bnxt_sw_mpc_tx_bd { + unsigned long handle; +}; + +#define SW_MPC_TXBD_RING_SIZE (sizeof(struct bnxt_sw_mpc_tx_bd) * TX_DESC_CNT) + #define BNXT_MPC_CRYPTO_CAP \ (FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE | FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE) @@ -42,11 +48,19 @@ void bnxt_alloc_mpc_info(struct bnxt *bp, u8 mpc_chnls_cap); void bnxt_free_mpc_info(struct bnxt *bp); int bnxt_mpc_tx_rings_in_use(struct bnxt *bp); int bnxt_mpc_cp_rings_in_use(struct bnxt *bp); +bool bnxt_napi_has_mpc(struct bnxt *bp, int i); +void bnxt_set_mpc_cp_ring(struct bnxt *bp, int bnapi_idx, + struct bnxt_cp_ring_info *cpr); void bnxt_trim_mpc_rings(struct bnxt *bp); void bnxt_calc_dflt_mpc_rings(struct bnxt *bp, int tx_nr_rings, int tx_nr_rings_per_tc, int rx_nr_rings, int *mpc_per_type, int *mpc_cp); void bnxt_set_dflt_mpc_rings(struct bnxt *bp); +void bnxt_init_mpc_ring_struct(struct bnxt *bp); +int bnxt_alloc_mpcs(struct bnxt *bp); +void bnxt_free_mpcs(struct bnxt *bp); +int bnxt_alloc_mpc_rings(struct bnxt *bp); +void bnxt_free_mpc_rings(struct bnxt *bp); #else static inline void bnxt_alloc_mpc_info(struct bnxt *bp, u8 mpc_chnls_cap) { @@ -66,6 +80,16 @@ static inline int bnxt_mpc_cp_rings_in_use(struct bnxt *bp) return 0; } +static inline bool bnxt_napi_has_mpc(struct bnxt *bp, int i) +{ + return false; +} + +static inline void bnxt_set_mpc_cp_ring(struct bnxt *bp, int bnapi_idx, + struct bnxt_cp_ring_info *cpr) +{ +} + static inline void bnxt_trim_mpc_rings(struct bnxt *bp) { } @@ -82,5 +106,27 @@ static inline void bnxt_calc_dflt_mpc_rings(struct bnxt *bp, int tx_nr_rings, static inline void bnxt_set_dflt_mpc_rings(struct bnxt *bp) { } + +static inline void bnxt_init_mpc_ring_struct(struct bnxt *bp) +{ +} + +static inline int bnxt_alloc_mpcs(struct bnxt *bp) +{ + return 0; +} + +static inline void bnxt_free_mpcs(struct bnxt *bp) +{ +} + +static inline int bnxt_alloc_mpc_rings(struct bnxt *bp) +{ + return 0; +} + +static inline void bnxt_free_mpc_rings(struct bnxt *bp) +{ +} #endif /* CONFIG_BNXT_TLS */ #endif /* BNXT_MPC_H */ -- 2.51.0