From: Tony Nguyen <anthony.l.nguyen@intel.com>
To: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, andrew+netdev@lunn.ch,
netdev@vger.kernel.org
Cc: Przemyslaw Korba <przemyslaw.korba@intel.com>,
anthony.l.nguyen@intel.com, aleksander.lobakin@intel.com,
konstantin.ilichev@intel.com, richardcochran@gmail.com,
poros@redhat.com, przemyslaw.kitszel@intel.com,
robert.malz@canonical.com, willemb@google.com,
Simon Horman <horms@kernel.org>, Rinitha S <sx.rinitha@intel.com>,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: [PATCH net 1/4] ice: fall back to SBQ when LL PHY timer interface times out
Date: Tue, 11 Aug 2026 17:09:14 -0700 [thread overview]
Message-ID: <20260812000918.220714-2-anthony.l.nguyen@intel.com> (raw)
In-Reply-To: <20260812000918.220714-1-anthony.l.nguyen@intel.com>
From: Przemyslaw Korba <przemyslaw.korba@intel.com>
The low-latency (LL) PHY timer interface relies on a tight, atomic poll
of the PF_SB_ATQBAL register with a 2ms timeout. After an NVM update /
EMPR, FW may need significantly longer than 2ms to start responding to
ATQBAL commands. The first PHY adjust or incval write issued by
ice_ptp_rebuild_owner() fails with -ETIMEDOUT.
Fix this by falling back to the existing SBQ-based PHY register write
path when LL times out. This makes sure PTP is initialized when FW takes
longer than expected to come back online.
Steps to reproduce:
./nvmupdate64e -if devlink -f
Update E810 card with nvmupdate64e, and observe dmesg errors:
Failed to write PHC increment value, status -110
PTP reset failed, error: -110 (-ETIMEDOUT)
Fixes: ef9a64c07294 ("ice: implement low latency PHY timer updates")
Signed-off-by: Przemyslaw Korba <przemyslaw.korba@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 38 +++++++++++----------
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 8e5f97835954..3a41c711e751 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -4808,15 +4808,12 @@ static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj)
!FIELD_GET(REG_LL_PROXY_H_EXEC, val),
10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
REG_LL_PROXY_H);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
- spin_unlock_irq(¶ms->atqbal_wq.lock);
- return err;
- }
-
spin_unlock_irq(¶ms->atqbal_wq.lock);
- return 0;
+ if (err)
+ ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
+
+ return err;
}
/**
@@ -4837,8 +4834,12 @@ static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
u8 tmr_idx;
int err;
- if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
- return ice_ptp_prep_phy_adj_ll_e810(hw, adj);
+ if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) {
+ err = ice_ptp_prep_phy_adj_ll_e810(hw, adj);
+ if (err != -ETIMEDOUT)
+ return err;
+ ice_debug(hw, ICE_DBG_PTP, "LL adj timed out, falling back to SBQ\n");
+ }
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -4901,15 +4902,12 @@ static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval)
!FIELD_GET(REG_LL_PROXY_H_EXEC, val),
10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
REG_LL_PROXY_H);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
- spin_unlock_irq(¶ms->atqbal_wq.lock);
- return err;
- }
-
spin_unlock_irq(¶ms->atqbal_wq.lock);
- return 0;
+ if (err)
+ ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
+
+ return err;
}
/**
@@ -4927,8 +4925,12 @@ static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
u8 tmr_idx;
int err;
- if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
- return ice_ptp_prep_phy_incval_ll_e810(hw, incval);
+ if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) {
+ err = ice_ptp_prep_phy_incval_ll_e810(hw, incval);
+ if (err != -ETIMEDOUT)
+ return err;
+ ice_debug(hw, ICE_DBG_PTP, "LL incval timed out, falling back to SBQ\n");
+ }
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
low = lower_32_bits(incval);
--
2.47.1
next prev parent reply other threads:[~2026-08-12 0:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 0:09 [PATCH net 0/4][pull request] Intel Wired LAN Driver Updates 2026-08-11 (ice, idpf) Tony Nguyen
2026-08-12 0:09 ` Tony Nguyen [this message]
2026-08-12 0:09 ` [PATCH net 2/4] ice: clear the default forwarding VSI rule when releasing a VSI Tony Nguyen
2026-08-12 0:09 ` [PATCH net 3/4] ice: acquire NVM lock around each flash read Tony Nguyen
2026-08-12 0:09 ` [PATCH net 4/4] idpf: add missing cpu_to_le32 in idpf_tx_splitq_build_flow_desc Tony Nguyen
2026-08-17 20:40 ` [PATCH net 0/4][pull request] Intel Wired LAN Driver Updates 2026-08-11 (ice, idpf) patchwork-bot+netdevbpf
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