From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2497930EF8F; Wed, 12 Aug 2026 10:50:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786531853; cv=none; b=uvdag+EN/qArZttfyePSd6KoE6FjU+Sd37pZBqtdxfuAzNh7rsc7ritm+K4LG0uyjkRDhLovae7iShgzy1D73PTZXIZQqWe1hpViw9bhZjjKxgJvaFZYXRqQrsYbbEXK7YJNSkxl12TrJfI/SoBeeqcGVIOGcW7/VFWRIZDuN/s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786531853; c=relaxed/simple; bh=l8e7mf5CTX1bJSjWPoqQB3jl5jYEmYnVga61pAP7NGE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mbfOPF5WY045LhfbDi7WyvbImYW7oY2K47xXBqBh5zLq25LRj7R4ztLqLGODVW5Me1RO1NlY2gQNNNwUA7lyYW2UVbNUEhYN9/aLRwOf+UYowbWw+8qg4JPaT+PlcHBkc6oSTvu2CstjzkzFrz+gj0f5SoZLkdyV4FHXNXEm4gA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=a8/7E823; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="a8/7E823" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1786531852; x=1818067852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l8e7mf5CTX1bJSjWPoqQB3jl5jYEmYnVga61pAP7NGE=; b=a8/7E823mC09tWuPUWdt0nWqMOtDRyTB0BzT2TNUSZtYqcHazK69lpoe CObNmEKswHZhTjP5FewTM7yekfWLA7B3kMZyUT9c5ypV+/8Nb+ZfE5Gu3 ckQlrtAsrEltxgdnyVn2kdeRF4Hjd0guZl2QCPi/Xbmsg8H6Vxv0JC8dk cS91H/wfeHQ/ieJKDqlUXkzky0jS6rvVm6H7VQFyzQh3t/ZSJ3mCL1szm Vv7K31lMqwslDWMrqB5L7904OqfHXJd8pDjaDQ1dT87kq0xp9zVnCyM1f MkT8NBWzkDaSL2nkFNLKiFdibcgUhrrCToUZV8qD2oJBdT2zTxJMPL6Fq Q==; X-CSE-ConnectionGUID: u0rlZIKHSpSTMJU3C9X76w== X-CSE-MsgGUID: Ru9W8DBtTcG7xCgIgmwuLQ== X-IronPort-AV: E=Sophos;i="6.25,219,1779174000"; d="scan'208";a="229147411" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Aug 2026 03:50:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 12 Aug 2026 03:50:50 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 12 Aug 2026 03:50:39 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v7 3/7] mtd: spi-nor: sfdp: expose the SFDP as a read-only NVMEM device Date: Wed, 12 Aug 2026 16:19:51 +0530 Message-ID: <20260812104955.485667-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260812104955.485667-1-manikandan.m@microchip.com> References: <20260812104955.485667-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The SPI NOR core already reads the SFDP tables during enumeration and caches them in nor->sfdp->dwords (see spi_nor_parse_sfdp()). Re-expose that cached data as a read-only NVMEM device, in on-flash byte order, rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets NVMEM cells reference any SFDP data: a fixed-layout for parameters at a known offset, or an nvmem-layout parser for vendor data whose location must be discovered at runtime. The device is only registered when an "sfdp" node is present in the device tree. Signed-off-by: Manikandan Muralidharan --- drivers/mtd/spi-nor/core.c | 78 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ccf4396cdcd0..0425af6e898f 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -3001,6 +3002,75 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; } +static int spi_nor_sfdp_reg_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct spi_nor *nor = priv; + struct sfdp *sfdp = nor->sfdp; + size_t sfdp_size = sfdp->num_dwords * sizeof(*sfdp->dwords); + + if (offset >= sfdp_size || bytes > sfdp_size - offset) + return -EINVAL; + + /* The cached SFDP is kept in on-flash (little-endian) byte order. */ + memcpy(val, (u8 *)sfdp->dwords + offset, bytes); + + return 0; +} + +/** + * spi_nor_register_sfdp_nvmem() - expose the SFDP as a read-only NVMEM device + * @nor: pointer to a 'struct spi_nor' + * + * Expose the whole SFDP, in on-flash byte order, as a read-only NVMEM device + * rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets + * generic (fixed-layout) or vendor (nvmem-layout) cells reference any SFDP + * data. The device is only registered when a child node with the "jedec,sfdp" + * compatible is described in the device tree. + * + * Return: 0 on success or if there is nothing to do, -errno otherwise. + */ +static int spi_nor_register_sfdp_nvmem(struct spi_nor *nor) +{ + struct device *dev = nor->dev; + struct nvmem_config config = { }; + struct nvmem_device *nvmem; + struct device_node *np; + + if (!nor->sfdp) + return 0; + + np = of_get_compatible_child(dev_of_node(dev), "jedec,sfdp"); + if (!np) + return 0; + + config.dev = dev; + config.of_node = np; + config.name = "sfdp"; + config.id = NVMEM_DEVID_AUTO; + config.owner = THIS_MODULE; + config.read_only = true; + config.word_size = 1; + config.stride = 1; + config.size = (int)(nor->sfdp->num_dwords * sizeof(*nor->sfdp->dwords)); + config.reg_read = spi_nor_sfdp_reg_read; + config.priv = nor; + + nvmem = devm_nvmem_register(dev, &config); + of_node_put(np); + if (IS_ERR(nvmem)) { + /* NVMEM support is optional. */ + if (PTR_ERR(nvmem) == -EOPNOTSUPP) + return 0; + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register SFDP NVMEM device\n"); + } + + dev_dbg(dev, "exposed %d-byte SFDP as an NVMEM device\n", config.size); + + return 0; +} + /** * spi_nor_late_init_params() - Late initialization of default flash parameters. * @nor: pointer to a 'struct spi_nor' @@ -3204,6 +3274,14 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } + /* + * Expose the SFDP table as an NVMEM device only when + * the flash actually provides one + */ + ret = spi_nor_register_sfdp_nvmem(nor); + if (ret) + return ret; + ret = spi_nor_late_init_params(nor); if (ret) return ret; -- 2.43.0