From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED9F54C9557 for ; Fri, 21 Aug 2026 15:24:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787325901; cv=none; b=XkHs67DzQ5fZ259Hp1b3QxfWvrHIjakgPRnpCwCx8woDDnX7EKm5l3Iuql9d9bXmLOGucnUwYQyNW4B1TOcZK2CEaIyI03LmZBLY9qv02TbZMKB8WrySNaaTDKdty1iQDR/gICdBnix7LOaeglZurgS9dOiCrmqfc3Ysw8kz+rk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787325901; c=relaxed/simple; bh=BWEJljClCLoMqdC5CrvRogdJO+tr/guzV0d1rSKboEs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A9PxSr2niai+4Bfeb/PvXefAiBkUiajWZpHs2c73noQ7rjvwv4SbkjFi1Z10eOv4urfJJ0Zq0FW08dGVnK5y+50jnt67xK/W775loJo5kugNBl29fKZ8ltPTgKx5+g+oIPkPnkd1LvvTLhscTKxX0Mz5K03StJ32GHNPKpXzGCU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=knM8MX0T; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="knM8MX0T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787325899; x=1818861899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BWEJljClCLoMqdC5CrvRogdJO+tr/guzV0d1rSKboEs=; b=knM8MX0Twl9QC5F54RCBZ5oCdwc0PyPBl9U6/0rAfp9BKBlEH+sQpwl6 lTGLqvNa1Nso8cLrBsXESR7idfBwYBuWl8q2OIWhmh+VrvWg31kdQUpJw hMPEQb1jMXuDT9shG+HbPQhSOalwwMTF6uQ/jbf5tdk/E+sT3KmO0oP/I R/ZLAfpXZjzV9tq3aGJkBG8Rk439msXOPXzKUwHhjAeTwA6gpo7BjssFO qjfKkK8rwJ+y3BHUB13hZLwVuofQ3Y9FIw2TtdMWgWPgSIdRCCJhaEe/I vYgatGb+aan3IedDBV3eo63cE0q0mAUIy4KnvsouJSOLXIw4rDj4wo8tj w==; X-CSE-ConnectionGUID: zmI02qdQQiG8Zoi4HJZ/Ew== X-CSE-MsgGUID: svPKHnyURO+B12RKLRJLxw== X-IronPort-AV: E=McAfee;i="6800,10657,11882"; a="91553203" X-IronPort-AV: E=Sophos;i="6.25,235,1779174000"; d="scan'208";a="91553203" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2026 08:24:58 -0700 X-CSE-ConnectionGUID: dbRnceBASMy97UvEKZn1Cg== X-CSE-MsgGUID: itlv4FlbTBS7AO1ie586oQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,235,1779174000"; d="scan'208";a="270602192" Received: from gnrd8.igk.intel.com (HELO GNRD8) ([10.123.232.137]) by orviesa005.jf.intel.com with ESMTP; 21 Aug 2026 08:24:57 -0700 From: Sergey Temerkhanov To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org Subject: [PATCH iwl-next v3 3/6] ice: dpll: Use switch statements to handle pin states Date: Fri, 21 Aug 2026 15:24:51 +0000 Message-ID: <20260821152454.3703979-4-sergey.temerkhanov@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260821152454.3703979-1-sergey.temerkhanov@intel.com> References: <20260821152454.3703979-1-sergey.temerkhanov@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use switch statements to handle pin states to make the code more readable. This also makes this code more future-proof, should any new states appear. This also changes how direction-mismatched state requests are handled in ice_dpll_sma_pin_state_set(). Previously, requesting CONNECTED on an INPUT-direction SMA pin or SELECTABLE on an OUTPUT-direction pin would fall through to ice_dpll_pin_disable() and return success. After this change those requests return -EINVAL without issuing a firmware command. Because the DPLL netlink core does not filter pin states by direction before calling the driver, this is a user-visible netlink API change. Signed-off-by: Sergey Temerkhanov Reviewed-by: Aleksandr Loktionov Reviewed-by: Przemyslaw Korba --- drivers/net/ethernet/intel/ice/ice_dpll.c | 72 ++++++++++++++++++----- 1 file changed, 57 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 4dcbbabee7aa..f4d6c247e96e 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -1338,10 +1338,12 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, ret = -EINVAL; switch (p->idx) { case ICE_DPLL_PIN_SW_1_IDX: - if (state == DPLL_PIN_STATE_CONNECTED) { + switch (state) { + case DPLL_PIN_STATE_CONNECTED: data &= ~ICE_SMA1_MASK; enable = true; - } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + break; + case DPLL_PIN_STATE_DISCONNECTED: /* Skip if U.FL1 is not active, setting TX_EN * while DIR_EN is set would also deactivate * the paired SMA1 output. @@ -1352,18 +1354,21 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, } data |= ICE_SMA1_TX_EN; enable = false; - } else { + break; + default: goto unlock; } target = p->output; type = ICE_DPLL_PIN_TYPE_OUTPUT; break; case ICE_DPLL_PIN_SW_2_IDX: - if (state == DPLL_PIN_STATE_SELECTABLE) { + switch (state) { + case DPLL_PIN_STATE_SELECTABLE: data |= ICE_SMA2_DIR_EN; data &= ~ICE_SMA2_UFL2_RX_DIS; enable = true; - } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + break; + case DPLL_PIN_STATE_DISCONNECTED: /* Skip if U.FL2 is not active, setting * UFL2_RX_DIS could also disable the paired * SMA2 input. @@ -1375,7 +1380,8 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, } data |= ICE_SMA2_UFL2_RX_DIS; enable = false; - } else { + break; + default: goto unlock; } target = p->input; @@ -1497,19 +1503,49 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, return -EBUSY; mutex_lock(&pf->dplls.lock); - if (!sma->active) { - ret = ice_dpll_sma_direction_set(sma, sma->direction, extack); - if (ret) + switch (state) { + case DPLL_PIN_STATE_SELECTABLE: + if (sma->direction == DPLL_PIN_DIRECTION_OUTPUT) { + enable = false; + ret = -EINVAL; + goto unlock; + } + enable = true; + break; + case DPLL_PIN_STATE_CONNECTED: + if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { + enable = false; + ret = -EINVAL; goto unlock; + } + enable = true; + break; + case DPLL_PIN_STATE_DISCONNECTED: + enable = false; + break; + default: + ret = -EINVAL; + goto unlock; } - if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { - enable = state == DPLL_PIN_STATE_SELECTABLE; + + switch (sma->direction) { + case DPLL_PIN_DIRECTION_INPUT: target = sma->input; type = ICE_DPLL_PIN_TYPE_INPUT; - } else { - enable = state == DPLL_PIN_STATE_CONNECTED; + break; + case DPLL_PIN_DIRECTION_OUTPUT: target = sma->output; type = ICE_DPLL_PIN_TYPE_OUTPUT; + break; + default: + ret = -EINVAL; + goto unlock; + } + + if (!sma->active) { + ret = ice_dpll_sma_direction_set(sma, sma->direction, extack); + if (ret) + goto unlock; } if (enable) @@ -4917,7 +4953,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.capabilities = caps; pin->pf = pf; pin->prop.board_label = ice_dpll_sw_pin_ufl[i]; - if (i == ICE_DPLL_PIN_SW_1_IDX) { + switch (i) { + case ICE_DPLL_PIN_SW_1_IDX: pin->direction = DPLL_PIN_DIRECTION_OUTPUT; pin_abs_idx = ICE_DPLL_PIN_SW_OUTPUT_ABS(i); pin->prop.freq_supported = @@ -4927,7 +4964,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.freq_supported_num = freq_supp_num; pin->input = NULL; pin->output = &d->outputs[pin_abs_idx]; - } else if (i == ICE_DPLL_PIN_SW_2_IDX) { + break; + case ICE_DPLL_PIN_SW_2_IDX: pin->direction = DPLL_PIN_DIRECTION_INPUT; pin_abs_idx = ICE_DPLL_PIN_SW_INPUT_ABS(i) + input_idx_offset; @@ -4940,6 +4978,10 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.capabilities = (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps); + break; + default: + dev_err(ice_pf_to_dev(pf), "Invalid U.FL pin index: %d\n", i); + return -EINVAL; } pin->muxed = &d->sma[i]; ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); -- 2.53.0