From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FABA3B9DA6 for ; Wed, 26 Aug 2026 09:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787737738; cv=none; b=Lly0QjD8LACS2HmiYDo+DCNcr1Q1We4bMa5zK0tg81wOsn2QHoK8cdDFEEhb7BW60cERTXRI0dfKjZssHQcUArrDcFhMSk75v4F6BkDoXOz8TW4kr4HpctccItAVkYl2OD0lL3vQ2nO37V+uWUr/p64A7xG9fm4tOsxOUjrh9Lc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787737738; c=relaxed/simple; bh=7+vt+NZZE3SQIPplBtEF9c84EljBe11G7WHirIUgDHY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p7izCwMeYzwZVR2J4C7g2rfPW5COpDlTFdO3BGcN16dNFvoCCGGat5KcPk9aWWYSLPNUWB0hRT0WFDIOXhxjSX5Iw3DyJeI6fDibjHoAAg79Kc9L09poaq6x6Ng/2ihWL7vDXWjk3gySPQMwMHhQ8P4Ni4o6Fl8o7I1x13E2Kuw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=e6HBsO0n; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e6HBsO0n" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787737736; x=1819273736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7+vt+NZZE3SQIPplBtEF9c84EljBe11G7WHirIUgDHY=; b=e6HBsO0nP+2heR55GQ62YXS+EmvJIeFlnMAe6vIr4wcFZWgA3dZq5HGo AOonmxX9I69VCj2qGURF4dJP0byZuy1/CqWgmNik6Sr8TsWwX1Aml0I3X TEJUxcAFcxmNWTNcLKnpa7SXpUIAT5FKOhl+Y6cvhNVIKKBsZDKMXo+qz A6Eo0z8J0cBTJCx7Vugj3PBZtC5enBUug8QYKik/mdmjhwqGxrGn5JZkP WwGCF7wHzJBqZBX24XX2BtQeKhZsksEualWku7vH9OmF/riqnuknEa4rH luFb+7Z0Lw5Zvx08SxnB77TGxtbxEy/Rb4CXY6BuuZt5sSuVYPONcTjUT w==; X-CSE-ConnectionGUID: hMDKK5CnRxS3CJ1wznVNvw== X-CSE-MsgGUID: HdWDzdWnRu6HurB19xQLtA== X-IronPort-AV: E=McAfee;i="6800,10657,11886"; a="88232951" X-IronPort-AV: E=Sophos;i="6.25,244,1779174000"; d="scan'208";a="88232951" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2026 02:48:53 -0700 X-CSE-ConnectionGUID: l/z/EqQJQFSu3a6pAf0g3Q== X-CSE-MsgGUID: zI/LtnL2Qqeo6tsJUnOAfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,244,1779174000"; d="scan'208";a="261404800" Received: from gnrd8.igk.intel.com (HELO GNRD8) ([10.123.232.137]) by fmviesa009.fm.intel.com with ESMTP; 26 Aug 2026 02:48:52 -0700 From: Sergey Temerkhanov To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org Subject: [PATCH iwl-next v4 2/6] ice: dpll: Rework multiplexed pin notifications Date: Wed, 26 Aug 2026 09:48:45 +0000 Message-ID: <20260826094849.4112016-3-sergey.temerkhanov@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260826094849.4112016-1-sergey.temerkhanov@intel.com> References: <20260826094849.4112016-1-sergey.temerkhanov@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use a pointer to the struct ice_dpll_pin to link multiplexed pins. This allows to simplify the selection logic. Signed-off-by: Sergey Temerkhanov Reviewed-by: Aleksandr Loktionov Reviewed-by: Przemyslaw Korba --- drivers/net/ethernet/intel/ice/ice_dpll.c | 60 +++++++++++------------ drivers/net/ethernet/intel/ice/ice_dpll.h | 1 + 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 9b3584fa43a9..4dcbbabee7aa 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -564,6 +564,29 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin, return ret; } +/** + * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change + * @changed: the SW pin that was explicitly changed (already notified by dpll core) + * + * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and + * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO + * expander, the paired pin's state may also change. Send a change + * notification for the peer pin so userspace consumers monitoring the + * peer via dpll netlink learn about the update. + * + * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is + * released. Uses __dpll_pin_change_ntf() because dpll_lock is + * still held by the dpll netlink layer. + */ +static void ice_dpll_sw_pin_notify_peer(struct ice_dpll_pin *changed) +{ + struct ice_dpll_pin *peer; + + peer = changed->muxed; + if (peer->pin) + __dpll_pin_change_ntf(peer->pin); +} + /** * ice_dpll_pin_store_state - updates the state of pin in SW bookkeeping * @pin: pointer to a pin @@ -1189,32 +1212,6 @@ ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv, extack, ICE_DPLL_PIN_TYPE_INPUT); } -/** - * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change - * @d: pointer to dplls struct - * @changed: the SW pin that was explicitly changed (already notified by dpll core) - * - * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and - * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO - * expander, the paired pin's state may also change. Send a change - * notification for the peer pin so userspace consumers monitoring the - * peer via dpll netlink learn about the update. - * - * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is - * released. Uses __dpll_pin_change_ntf() because dpll_lock is - * still held by the dpll netlink layer. - */ -static void ice_dpll_sw_pin_notify_peer(struct ice_dplls *d, - struct ice_dpll_pin *changed) -{ - struct ice_dpll_pin *peer; - - peer = (changed >= d->sma && changed < d->sma + ICE_DPLL_PIN_SW_NUM) ? - &d->ufl[changed->idx] : &d->sma[changed->idx]; - if (peer->pin) - __dpll_pin_change_ntf(peer->pin); -} - /** * ice_dpll_sma_direction_set - set direction of SMA pin * @p: pointer to a pin @@ -1276,7 +1273,7 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, * backing pin when U.FL becomes inactive because the SMA pin may * still be using it. */ - peer = &d->ufl[p->idx]; + peer = p->muxed; if (peer->active) { struct ice_dpll_pin *target; enum ice_dpll_pin_type type; @@ -1406,7 +1403,7 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, p); + ice_dpll_sw_pin_notify_peer(p); return ret; } @@ -1526,7 +1523,7 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, sma); + ice_dpll_sw_pin_notify_peer(sma); return ret; } @@ -1723,7 +1720,7 @@ ice_dpll_pin_sma_direction_set(const struct dpll_pin *pin, void *pin_priv, ret = ice_dpll_sma_direction_set(p, direction, extack); mutex_unlock(&pf->dplls.lock); if (!ret) - ice_dpll_sw_pin_notify_peer(&pf->dplls, p); + ice_dpll_sw_pin_notify_peer(p); return ret; } @@ -4909,6 +4906,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) if (pin->input->ref_sync) pin->ref_sync = pin->input->ref_sync - pin_abs_idx; pin->output = &d->outputs[ICE_DPLL_PIN_SW_OUTPUT_ABS(i)]; + pin->muxed = &d->ufl[i]; + ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } for (i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { @@ -4942,6 +4941,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps); } + pin->muxed = &d->sma[i]; ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethernet/intel/ice/ice_dpll.h index bce0bea9a664..f7e6680d124c 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -76,6 +76,7 @@ struct ice_dpll_pin { s32 phase_adjust; struct ice_dpll_pin *input; struct ice_dpll_pin *output; + struct ice_dpll_pin *muxed; enum dpll_pin_direction direction; s64 phase_offset; u8 status; -- 2.53.0