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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b4e2c1af7sm110839735e9.15.2026.08.28.00.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 00:48:56 -0700 (PDT) Date: Fri, 28 Aug 2026 08:48:54 +0100 From: David Laight To: aslan.jnn@gmail.com Cc: Raju Rangoju , Prashanth Kumar K R , netdev@vger.kernel.org, Thomas.Lendacky@amd.com, Simon Horman , Jakub Kicinski Subject: Re: [PATCH net v2] net: amd-xgbe: support receiving packets with bad FCS Message-ID: <20260828084854.67cb625a@pumpkin> In-Reply-To: <20260827233527.71620-1-aslan.jnn@gmail.com> References: <20260821213646.7bbb94d6@pumpkin> <20260827233527.71620-1-aslan.jnn@gmail.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 28 Aug 2026 09:35:27 +1000 aslan.jnn@gmail.com wrote: > Hi David, > > I agree with your first statement. I've just submitted the v3 of this patch > which removes the DCRCC unsetting on xgbe_disable_rx. > > And thanks for your input for setting MAC_RCR non-atomically like that! I > didn't thought much about it before, to be honest. Will try handling that > on the next submission. I'm assuming there is some kind of reset that sets the MAC_RCR register to all zero? If so you don't need to change it at all. If not then you need to absolutely ensure all bits are initialised to valid values before the receiver is enabled. David > > James > > On Fri, Aug 21, 2026 at 9:36:46PM +0100, David Laight wrote: > > On Wed, 19 Aug 2026 19:16:56 +1000 > > James wrote: > > > > > > You can delete the line in the disable function that turns it off. > > > > But, really, you should be setting the required MAC_RCR bits in a single > > write. > > Doing RMW sequences on the hardware registers for each bit is really wrong. > > You also need to start with a known value for all the bits, otherwise > > 'silly' things can happen is (say) some bios boot code set bits you don't > > otherwise change. > > > > David