From: Michael Chan <michael.chan@broadcom.com>
To: davem@davemloft.net
Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, andrew+netdev@lunn.ch,
pavan.chebbi@broadcom.com, andrew.gospodarek@broadcom.com,
Kalesh AP <kalesh-anakkur.purayil@broadcom.com>,
Scott Branden <scott.branden@broadcom.com>
Subject: [PATCH net 4/4] bnxt_en: Re-write the BARs following any type of PCIe errors
Date: Sun, 30 Aug 2026 19:43:42 -0700 [thread overview]
Message-ID: <20260831024342.2161156-5-michael.chan@broadcom.com> (raw)
In-Reply-To: <20260831024342.2161156-1-michael.chan@broadcom.com>
From: Pavan Chebbi <pavan.chebbi@broadcom.com>
Currently the driver zeroes the BARs only when fatal PCIe errors
are reported so that pci_restore_state() restores it. However
firmware handles both fatal and non-fatal errors the same way when
it sees the slot reset resulting from the PCI_ERS_RESULT_NEED_RESET
return code from the driver. This means that we must re-write the
BARs post recovery even during non-fatal errors. Otherwise we will
see that every MMIO access returns all-ones and the firmware appears
dead.
Zero-out the BARs during PCIe error recovery regardless of type of
PCIe error.
Fixes: f75d9a0aa967 ("bnxt_en: Re-write PCI BARs after PCI fatal error.")
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index c3d561ac53dc..09fed8784a2a 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -17564,7 +17564,7 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
netdev_info(bp->dev, "PCI Slot Reset\n");
- if (test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state)) {
+ if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state)) {
/* After DPC, the chip should return CRS when the vendor ID
* config register is read until it is ready. On all chips,
* this is not happening reliably so add a 5-second delay as a
@@ -17580,17 +17580,15 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
"Cannot re-enable PCI device after reset.\n");
} else {
pci_set_master(pdev);
- /* Upon fatal error, our device internal logic that latches to
+ /* Upon PCIe error, our device internal logic that latches to
* BAR value is getting reset and will restore only upon
* rewriting the BARs.
*
* As pci_restore_state() does not re-write the BARs if the
* value is same as saved value earlier, driver needs to
- * write the BARs to 0 to force restore, in case of fatal error.
+ * write the BARs to 0 to force restore.
*/
- if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
- &bp->state))
- bnxt_clear_bars(pdev);
+ bnxt_clear_bars(pdev);
pci_restore_state(pdev);
bnxt_inv_fw_health_reg(bp);
--
2.51.0
next prev parent reply other threads:[~2026-08-31 2:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-31 2:43 [PATCH net 0/4] bnxt_en: Bug fixes Michael Chan
2026-08-31 2:43 ` [PATCH net 1/4] bnxt_en: Fix ring accounting underflow when rings are constrained Michael Chan
2026-09-02 5:46 ` [net,1/4] " netdev-bot+sashiko
2026-08-31 2:43 ` [PATCH net 2/4] bnxt_en: Add bnxt_clear_bars() helper Michael Chan
2026-09-01 22:09 ` Joe Damato
2026-08-31 2:43 ` [PATCH net 3/4] bnxt_en: Fix driver init in kdump kernel Michael Chan
2026-09-01 22:20 ` Joe Damato
2026-09-02 5:46 ` [net,3/4] " netdev-bot+sashiko
2026-08-31 2:43 ` Michael Chan [this message]
2026-09-01 22:15 ` [PATCH net 4/4] bnxt_en: Re-write the BARs following any type of PCIe errors Joe Damato
2026-09-02 5:46 ` [net,4/4] " netdev-bot+sashiko
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