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chris.packham@alliedtelesis.co.nz, daniel@makrotopia.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH net-next v15 11/13] net: mdio: realtek-rtl9300: Add support for RTL838x Date: Mon, 31 Aug 2026 16:34:37 +0200 Message-ID: <20260831143439.2404484-12-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831143439.2404484-1-markus.stockhausen@gmx.de> References: <20260831143439.2404484-1-markus.stockhausen@gmx.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:kVTVWyeoAGcYl74dx4c0+srVVO1zQ2KKCHkV+Np3dzphsUbkyoV J3SotnOyBC5w+ogJCBWRSReDypQKoX0bqnixLctXVqLEMSD4KL3Bw1edXnmylk62uM/MwL1 q7M4eCskVsAD/xHQgu1eGJ/So2oo2asMgkMb4ZfEsXLy40XkKTlJ6pMQlZhP2Ox+mc2Lf6K mnWaCgwA9kFCxHhyAOkQw== X-Spam-Flag: NO UI-OutboundReport: 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kW5H0WIYvtI3vnHogfDb7yrpfZDdqb+4bGCpUD43rywbPRG4VtVKNwbrYQ8W2dmJVW69sK6+9 WKfPJVDh30NdL7yVev5h7rWdF5A1XP+m1lnGQFXQZdBM5qmQdKaTLNsCBzNe/3cOg6FbbhVuC wldvNXK9Ius2u2hxkyzE/N5zQtt8W3bZmVmdGRF3cj10Ak7zv1o/N8kTPU/aB8Psu0qg9sCun DKQgILWqzwBha5Zq9xt3xLTZqgt+lGUsDh0mu5vCcoVYNfLBqCaPFjFPStayQyJF80gk3zvJk GtYVL9cB9sBEjLQU6Mbo0As The MDIO driver has been prepared for multiple device support. Add all required bits for the RTL838x (aka maple) series. This is straightforward but some things are worth mentioning. - The device has a lot in common with the RTL930x series. It has 28 ports, 4096 (Realtek) pages and 4 MMIO registers. With this a lot of the existing RTL9300 defines could be reused. But to avoid confusion and for better readability duplicate the defines with a proper prefix. - The MDIO engine has no fail bit. Thus the mask is set to zero. - There is only one SMI bus for 1G PHYs. No bus_map_base register exists. - The setup_controller() function needs no C45 configuration as polling only works in C22 mode - The PHY access must be activated by a special register flag. Signed-off-by: Markus Stockhausen =2D-- drivers/net/mdio/mdio-realtek-rtl9300.c | 108 ++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/md= io-realtek-rtl9300.c index b90972c1dc6a..57ab89afb9e5 100644 =2D-- a/drivers/net/mdio/mdio-realtek-rtl9300.c +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -126,6 +126,28 @@ #include #include =20 +#define RTL8380_NUM_BUSES 1 +#define RTL8380_NUM_PAGES 4096 +#define RTL8380_NUM_PORTS 28 +#define RTL8380_SMI_GLB_CTRL 0xa100 +#define RTL8380_SMI_PHY_PATCH_DONE BIT(15) +#define RTL8380_SMI_ACCESS_PHY_CTRL_0 0xa1b8 +#define RTL8380_SMI_ACCESS_PHY_CTRL_1 0xa1bc +#define RTL8380_PHY_CTRL_REG_ADDR GENMASK(24, 20) +#define RTL8380_PHY_CTRL_PARK_PAGE GENMASK(19, 15) +#define RTL8380_PHY_CTRL_MAIN_PAGE GENMASK(14, 3) +#define RTL8380_PHY_CTRL_WRITE BIT(2) +#define RTL8380_PHY_CTRL_READ 0 +#define RTL8380_PHY_CTRL_TYPE_C45 BIT(1) +#define RTL8380_PHY_CTRL_TYPE_C22 0 +#define RTL8380_PHY_CTRL_FAIL 0 /* no fail indicator */ +#define RTL8380_SMI_ACCESS_PHY_CTRL_2 0xa1c0 +#define RTL8380_PHY_CTRL_INDATA GENMASK(31, 16) +#define RTL8380_PHY_CTRL_DATA GENMASK(15, 0) +#define RTL8380_SMI_ACCESS_PHY_CTRL_3 0xa1c4 +#define RTL8380_SMI_POLL_CTRL 0xa17c +#define RTL8380_SMI_PORT0_5_ADDR_CTRL 0xa1c8 + #define RTL9300_NUM_BUSES 4 #define RTL9300_NUM_PAGES 4096 #define RTL9300_NUM_PORTS 28 @@ -353,6 +375,60 @@ static int otto_emdio_write_cmd(struct mii_bus *bus, = u32 cmd, return otto_emdio_run_cmd(bus, cmd | priv->info->cmd_write, cmd_data); } =20 +static int otto_emdio_8380_read_c22(struct mii_bus *bus, int port, int re= gnum, u32 *value) +{ + struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); + struct otto_emdio_cmd_regs cmd_data =3D { + .c22_data =3D FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) | + FIELD_PREP(RTL8380_PHY_CTRL_PARK_PAGE, 0x1f) | + FIELD_PREP(RTL8380_PHY_CTRL_MAIN_PAGE, priv->page[port]), + .io_data =3D FIELD_PREP(RTL8380_PHY_CTRL_INDATA, port), + }; + + return otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, &cmd_data, + RTL8380_PHY_CTRL_DATA, value); +} + +static int otto_emdio_8380_write_c22(struct mii_bus *bus, int port, int r= egnum, u16 value) +{ + struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); + struct otto_emdio_cmd_regs cmd_data =3D { + .c22_data =3D FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) | + FIELD_PREP(RTL8380_PHY_CTRL_PARK_PAGE, 0x1f) | + FIELD_PREP(RTL8380_PHY_CTRL_MAIN_PAGE, priv->page[port]), + .io_data =3D FIELD_PREP(RTL8380_PHY_CTRL_INDATA, value), + .port_mask_low =3D BIT(port), + }; + + return otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, &cmd_data); +} + +static int otto_emdio_8380_read_c45(struct mii_bus *bus, int port, + int dev_addr, int regnum, u32 *value) +{ + struct otto_emdio_cmd_regs cmd_data =3D { + .c45_data =3D FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) | + FIELD_PREP(PHY_CTRL_MMD_REG, regnum), + .io_data =3D FIELD_PREP(RTL8380_PHY_CTRL_INDATA, port), + }; + + return otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, &cmd_data, + RTL8380_PHY_CTRL_DATA, value); +} + +static int otto_emdio_8380_write_c45(struct mii_bus *bus, int port, + int dev_addr, int regnum, u16 value) +{ + struct otto_emdio_cmd_regs cmd_data =3D { + .c45_data =3D FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) | + FIELD_PREP(PHY_CTRL_MMD_REG, regnum), + .io_data =3D FIELD_PREP(RTL8380_PHY_CTRL_INDATA, value), + .port_mask_low =3D BIT(port), + }; + + return otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, &cmd_data); +} + static int otto_emdio_9300_read_c22(struct mii_bus *bus, int port, int re= gnum, u32 *value) { struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); @@ -586,6 +662,15 @@ static int otto_emdio_setup_topology(struct otto_emdi= o_priv *priv) return 0; } =20 +static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv) +{ + /* + * PHY_PATCH_DONE enables PHY control via SoC. This is required for PHY = access, including + * patching and must be set before the PHYs are probed. + */ + return regmap_set_bits(priv->regmap, RTL8380_SMI_GLB_CTRL, RTL8380_SMI_P= HY_PATCH_DONE); +} + static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv) { u32 glb_ctrl_mask =3D 0, glb_ctrl_val =3D 0; @@ -873,6 +958,28 @@ static int otto_emdio_probe(struct platform_device *p= dev) return 0; } =20 +static const struct otto_emdio_info otto_emdio_8380_info =3D { + .addr_map_base =3D RTL8380_SMI_PORT0_5_ADDR_CTRL, + .cmd_fail =3D RTL8380_PHY_CTRL_FAIL, + .cmd_read =3D RTL8380_PHY_CTRL_READ, + .cmd_write =3D RTL8380_PHY_CTRL_WRITE, + .cmd_regs =3D { + .c22_data =3D RTL8380_SMI_ACCESS_PHY_CTRL_1, + .c45_data =3D RTL8380_SMI_ACCESS_PHY_CTRL_3, + .io_data =3D RTL8380_SMI_ACCESS_PHY_CTRL_2, + .port_mask_low =3D RTL8380_SMI_ACCESS_PHY_CTRL_0, + }, + .num_buses =3D RTL8380_NUM_BUSES, + .num_pages =3D RTL8380_NUM_PAGES, + .num_ports =3D RTL8380_NUM_PORTS, + .poll_ctrl =3D RTL8380_SMI_POLL_CTRL, + .setup_controller =3D otto_emdio_8380_setup_controller, + .read_c22 =3D otto_emdio_8380_read_c22, + .read_c45 =3D otto_emdio_8380_read_c45, + .write_c22 =3D otto_emdio_8380_write_c22, + .write_c45 =3D otto_emdio_8380_write_c45, +}; + static const struct otto_emdio_info otto_emdio_9300_info =3D { .addr_map_base =3D RTL9300_SMI_PORT0_5_ADDR_CTRL, .bus_map_base =3D RTL9300_SMI_PORT0_15_POLLING_SEL, @@ -923,6 +1030,7 @@ static const struct otto_emdio_info otto_emdio_9310_i= nfo =3D { }; =20 static const struct of_device_id otto_emdio_ids[] =3D { + { .compatible =3D "realtek,rtl8380-mdio", .data =3D &otto_emdio_8380_inf= o }, { .compatible =3D "realtek,rtl9301-mdio", .data =3D &otto_emdio_9300_inf= o }, { .compatible =3D "realtek,rtl9311-mdio", .data =3D &otto_emdio_9310_inf= o }, {} =2D-=20 2.55.0