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chris.packham@alliedtelesis.co.nz, daniel@makrotopia.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH net-next v15 12/13] net: mdio: realtek-rtl9300: Add support for RTL839x Date: Mon, 31 Aug 2026 16:34:38 +0200 Message-ID: <20260831143439.2404484-13-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831143439.2404484-1-markus.stockhausen@gmx.de> References: <20260831143439.2404484-1-markus.stockhausen@gmx.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:ubbSVk1sykregjt5Inl11CF+ifHveymx9QJc5wWscW7gsayLmvb OcFfdYcAwEDZiIsjT+xW6fZ7DCVG8vtWJd+KLjOogmdxULuZSRKmFfaAfKbUwGg/6g9aMGU wB1mKmCoDdoNQlNsB7gP7ZqJeA3mveWWqC0gwn1OyrT7zoV9TJuh0rE6ovtc85MG7tcGS/S o7os7gbu/2vCZDgVztw0w== X-Spam-Flag: NO UI-OutboundReport: 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Add all required bits for the RTL839x (aka cypress) series. This is straightforwar= d but some things are worth mentioning. - The device has a lot in common with the RTL931x series. It has 8192 (Realtek) pages and 7 MMIO registers. - There are two SMI buses for 1G PHYs. Neither the bus nor address map registers exist. - The hardware has not much to configure. So the setup_controller() function is not needed. - The bit specific registers (polling & port_mask) are 2x32 bit wide. The ports 0..31 got to and the ports 32..51 go to . - C22 read/write functions must be called with PARK_PAGE =3D 0. Keep code clean and avoid setting it to zero, matching the behavior of the RTL9310 logic. - As per SDK the broadcast register allows to write to multiple ports at the same time. Unlike RTL9310 where this is filled with a bit mask for the current port RTL8390 does not use it for normal reads/writes. It is simply set to 0 like the SDK does. - The SDK fills the EXT_PAGE register with 0x1ff for C22 access and with 0x0 for C45 access. The reason for this is currently unknown and a meaningful name can not be given. Align the driver coding with the RTL9300_PHY_CTRL_PARK_PAGE settings and simply fill the hardcoded value. Signed-off-by: Markus Stockhausen =2D-- drivers/net/mdio/mdio-realtek-rtl9300.c | 102 ++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/md= io-realtek-rtl9300.c index 57ab89afb9e5..86b2040fa333 100644 =2D-- a/drivers/net/mdio/mdio-realtek-rtl9300.c +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -148,6 +148,28 @@ #define RTL8380_SMI_POLL_CTRL 0xa17c #define RTL8380_SMI_PORT0_5_ADDR_CTRL 0xa1c8 =20 +#define RTL8390_NUM_BUSES 2 +#define RTL8390_NUM_PAGES 8192 +#define RTL8390_NUM_PORTS 52 +#define RTL8390_BCAST_PHYID_CTRL 0x03ec +#define RTL8390_PHYREG_ACCESS_CTRL 0x03dc +#define RTL8390_PHY_CTRL_REG_ADDR GENMASK(9, 5) +#define RTL8390_PHY_CTRL_MAIN_PAGE GENMASK(22, 10) +#define RTL8390_PHY_CTRL_FAIL BIT(1) +#define RTL8390_PHY_CTRL_WRITE BIT(3) +#define RTL8390_PHY_CTRL_READ 0 +#define RTL8390_PHY_CTRL_TYPE_C45 BIT(2) +#define RTL8390_PHY_CTRL_TYPE_C22 0 +#define RTL8390_PHYREG_CTRL 0x03e0 +#define RTL8390_PHY_CTRL_EXT_PAGE GENMASK(8, 0) +#define RTL8390_PHYREG_DATA_CTRL 0x03f0 +#define RTL8390_PHY_CTRL_INDATA GENMASK(31, 16) +#define RTL8390_PHY_CTRL_DATA GENMASK(15, 0) +#define RTL8390_PHYREG_MMD_CTRL 0x03f4 +#define RTL8390_PHYREG_PORT_CTRL_LOW 0x03e4 +#define RTL8390_PHYREG_PORT_CTRL_HIGH 0x03e8 +#define RTL8390_SMI_PORT_POLLING_CTRL 0x03fc + #define RTL9300_NUM_BUSES 4 #define RTL9300_NUM_PAGES 4096 #define RTL9300_NUM_PORTS 28 @@ -429,6 +451,62 @@ static int otto_emdio_8380_write_c45(struct mii_bus *= bus, int port, return otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, &cmd_data); } =20 +static int otto_emdio_8390_read_c22(struct mii_bus *bus, int port, int re= gnum, u32 *value) +{ + struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); + struct otto_emdio_cmd_regs cmd_data =3D { + .c22_data =3D FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) | + FIELD_PREP(RTL8390_PHY_CTRL_MAIN_PAGE, priv->page[port]), + .ext_page =3D FIELD_PREP(RTL8390_PHY_CTRL_EXT_PAGE, 0x1ff), + .io_data =3D FIELD_PREP(RTL8390_PHY_CTRL_INDATA, port), + }; + + return otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, &cmd_data, + RTL8390_PHY_CTRL_DATA, value); +} + +static int otto_emdio_8390_write_c22(struct mii_bus *bus, int port, int r= egnum, u16 value) +{ + struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); + struct otto_emdio_cmd_regs cmd_data =3D { + .c22_data =3D FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) | + FIELD_PREP(RTL8390_PHY_CTRL_MAIN_PAGE, priv->page[port]), + .ext_page =3D FIELD_PREP(RTL8390_PHY_CTRL_EXT_PAGE, 0x1ff), + .io_data =3D FIELD_PREP(RTL8390_PHY_CTRL_INDATA, value), + .port_mask_high =3D (u32)(BIT_ULL(port) >> 32), + .port_mask_low =3D (u32)(BIT_ULL(port)), + }; + + return otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, &cmd_data); +} + +static int otto_emdio_8390_read_c45(struct mii_bus *bus, int port, + int dev_addr, int regnum, u32 *value) +{ + struct otto_emdio_cmd_regs cmd_data =3D { + .c45_data =3D FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) | + FIELD_PREP(PHY_CTRL_MMD_REG, regnum), + .io_data =3D FIELD_PREP(RTL8390_PHY_CTRL_INDATA, port), + }; + + return otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, &cmd_data, + RTL8390_PHY_CTRL_DATA, value); +} + +static int otto_emdio_8390_write_c45(struct mii_bus *bus, int port, + int dev_addr, int regnum, u16 value) +{ + struct otto_emdio_cmd_regs cmd_data =3D { + .c45_data =3D FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) | + FIELD_PREP(PHY_CTRL_MMD_REG, regnum), + .io_data =3D FIELD_PREP(RTL8390_PHY_CTRL_INDATA, value), + .port_mask_high =3D (u32)(BIT_ULL(port) >> 32), + .port_mask_low =3D (u32)(BIT_ULL(port)), + }; + + return otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, &cmd_data); +} + static int otto_emdio_9300_read_c22(struct mii_bus *bus, int port, int re= gnum, u32 *value) { struct otto_emdio_priv *priv =3D otto_emdio_bus_to_priv(bus); @@ -980,6 +1058,29 @@ static const struct otto_emdio_info otto_emdio_8380_= info =3D { .write_c45 =3D otto_emdio_8380_write_c45, }; =20 +static const struct otto_emdio_info otto_emdio_8390_info =3D { + .cmd_fail =3D RTL8390_PHY_CTRL_FAIL, + .cmd_read =3D RTL8390_PHY_CTRL_READ, + .cmd_write =3D RTL8390_PHY_CTRL_WRITE, + .cmd_regs =3D { + .broadcast =3D RTL8390_BCAST_PHYID_CTRL, + .c22_data =3D RTL8390_PHYREG_ACCESS_CTRL, + .c45_data =3D RTL8390_PHYREG_MMD_CTRL, + .ext_page =3D RTL8390_PHYREG_CTRL, + .io_data =3D RTL8390_PHYREG_DATA_CTRL, + .port_mask_low =3D RTL8390_PHYREG_PORT_CTRL_LOW, + .port_mask_high =3D RTL8390_PHYREG_PORT_CTRL_HIGH, + }, + .num_buses =3D RTL8390_NUM_BUSES, + .num_pages =3D RTL8390_NUM_PAGES, + .num_ports =3D RTL8390_NUM_PORTS, + .poll_ctrl =3D RTL8390_SMI_PORT_POLLING_CTRL, + .read_c22 =3D otto_emdio_8390_read_c22, + .read_c45 =3D otto_emdio_8390_read_c45, + .write_c22 =3D otto_emdio_8390_write_c22, + .write_c45 =3D otto_emdio_8390_write_c45, +}; + static const struct otto_emdio_info otto_emdio_9300_info =3D { .addr_map_base =3D RTL9300_SMI_PORT0_5_ADDR_CTRL, .bus_map_base =3D RTL9300_SMI_PORT0_15_POLLING_SEL, @@ -1031,6 +1132,7 @@ static const struct otto_emdio_info otto_emdio_9310_= info =3D { =20 static const struct of_device_id otto_emdio_ids[] =3D { { .compatible =3D "realtek,rtl8380-mdio", .data =3D &otto_emdio_8380_inf= o }, + { .compatible =3D "realtek,rtl8391-mdio", .data =3D &otto_emdio_8390_inf= o }, { .compatible =3D "realtek,rtl9301-mdio", .data =3D &otto_emdio_9300_inf= o }, { .compatible =3D "realtek,rtl9311-mdio", .data =3D &otto_emdio_9310_inf= o }, {} =2D-=20 2.55.0