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This series adds a DPLL subsystem driver for the SiTime SiT95316 and=0A= SiT95317 I2C clock generators. Each device integrates four PLLs with=0A= automatic reference selection and on-chip TDC phase-offset measurement,=0A= and is used for synchronization in telecom, networking, and data-center=0A= timing.=0A= =0A= The series contains the device-tree binding, the driver under=0A= drivers/dpll/sit9531x/, and the MAINTAINERS entry.=0A= =0A= v1: https://lore.kernel.org/netdev/20260511211143.19792-1-arouhi@sitime.com= /=0A= v2: https://lore.kernel.org/netdev/20260520191943.73938-1-arouhi@sitime.com= /=0A= v3: https://lore.kernel.org/netdev/20260731180951.65725-1-arouhi@sitime.com= /=0A= v4: https://lore.kernel.org/netdev/20260806232439.27551-1-arouhi@sitime.com= /=0A= v5: https://lore.kernel.org/netdev/20260810230439.22866-1-arouhi@sitime.com= /=0A= v6: https://lore.kernel.org/netdev/20260812175337.18155-1-arouhi@sitime.com= /=0A= v7: https://lore.kernel.org/netdev/20260815221919.64226-1-arouhi@sitime.com= /=0A= =0A= The driver was a single 5.6k-line patch through v7. Vadim and Ivan asked=0A= for it to be split into logical parts, with the first zl3073x series as=0A= the model, so v8 introduces it feature by feature instead:=0A= =0A= 1-2 bindings: vendor prefix, then the device schema=0A= 3 basic support: paged regmap, variant detection, probe=0A= 4 DPLL types and pin properties from system firmware=0A= 5 register the DPLL devices and pins, and keep their state=0A= 6 input pin state on a DPLL, with the pin-state contract=0A= 7 input pin priority=0A= 8 pin frequency, both directions=0A= 9 output pin state (mute)=0A= 10 output phase adjust=0A= 11 esync on outputs=0A= 12 phase offset through the TDC=0A= 13 fractional frequency offset of the selected reference=0A= 14 the inter-PLL sync net as a pair of pins=0A= 15 optional device-tree overrides for two board facts=0A= =0A= The two bindings patches come first, so the driver never matches on a=0A= compatible string before the schema that describes it is in the tree.=0A= =0A= Each of the thirteen driver patches was built on its own, with W=3D1 on=0A= x86_64 and i386, and is sparse clean. Each one also links: no patch=0A= calls something that a later patch introduces, so the module builds at=0A= every step of the series and a bisect cannot land on a tree that fails=0A= to compile.=0A= =0A= The split makes no functional change of its own. The tree this series=0A= ends at compiles to objects byte-identical to the tree the single patch=0A= produced once the fixes below are applied to it.=0A= =0A= Changes in v8:=0A= =0A= - Split the driver patch into the thirteen patches listed above.=0A= =0A= - Advertise automatic mode only. v7 mapped DPLL_MODE_MANUAL onto the=0A= chip's free-run bit and then refused DPLL_PIN_STATE_CONNECTED on=0A= input pins, so it offered the mode whose one purpose is manual=0A= selection and refused the only request that mode exists for.=0A= Free-run selects no input at all, so on this device it is a lock=0A= state, not a selection mode. v8 advertises AUTOMATIC only and=0A= refuses anything else from .mode_set(), which now clears the outer=0A= loop disable bit so a PLL left free-running by the loaded=0A= configuration returns to selecting from the priority table.=0A= Free-run is reported through lock status as UNLOCKED.=0A= =0A= The device can also pin one reference while the loop keeps running,=0A= so real MANUAL support is possible later. It is left out here=0A= because the mode mapping becomes ABI once merged, and it belongs in=0A= the same series as the userspace that needs it rather than being=0A= approximated now.=0A= =0A= - State the pin-state contract once, above the pin ops, and let the=0A= two selection-role pins share one implementation of it. The driver=0A= had five ops tables and five hand-written encodings of the same=0A= state machine, and every review round has found another place where=0A= two of them disagreed. This closes several findings at once:=0A= CONNECTED reported while the outer loop was disabled, membership=0A= taken from the shared-receiver refcount rather than from the=0A= priority table, SELECTABLE on an INTSYNC destination userspace had=0A= disconnected, .prio_set() inserting a source that was never in the=0A= table, and .prio_remove() returning 0 when the disconnect would=0A= have emptied it. The last two are now -EINVAL and -EBUSY.=0A= =0A= - Report LOCKED_HO_ACQ only once the holdover estimate is valid. It=0A= was asserted whenever the loop was locked, without reading the bit=0A= that says the device has accumulated a frequency estimate good=0A= enough to fall back on. That bit is distinct from the one that says=0A= the PLL has already switched over to holdover.=0A= =0A= - Fix the 32-bit build. The output phase adjust reduced a negative=0A= request modulo the output period with % on two u64 values, leaving=0A= the module with an undefined __umoddi3; it now uses div64_u64_rem(),=0A= which the rest of the arithmetic there already uses. Reported by=0A= Jakub Kicinski.=0A= =0A= - Correct the register model comment: the page selector is at 0xFF and=0A= a page holds 256 registers, as the definitions right below the=0A= comment already said. Reported by Ivan Vecera.=0A= =0A= - Type ordinary clock outputs as DPLL_PIN_TYPE_EXT instead of=0A= DPLL_PIN_TYPE_GNSS, which claimed a GNSS-disciplined timing port.=0A= Advertise a phase-adjust range on outputs only, and drop the input=0A= pins' .phase_adjust_get with it: inputs have no .phase_adjust_set,=0A= so a non-zero range promised something every set would refuse.=0A= =0A= - Always issue the loop lock in the programming commit, so a transient=0A= I2C error cannot leave the chip in PRG_CMD with its loops open. Undo=0A= the global enable when the INTSYNC enable fails partway. Take=0A= multiop_lock before testing the selected reference in the frequency=0A= offset getter, as the sibling phase-offset getter already does.=0A= =0A= - Latch every read of the chip's debug block the way the phase read=0A= does. That block returns a sample of an internal measurement tap,=0A= selected by a read code and latched by reading a trigger register.=0A= The generic helper read the trigger once where the phase path reads=0A= it three times, and a single read returns the previous latch. On=0A= hardware this showed as a frequency offset that would not move while=0A= a phase measurement of the same PLL tracked a temperature step=0A= cleanly.=0A= =0A= - Report which PLLs came up and which EEPROM profile was loaded, and=0A= warn when a PLL drives outputs without having reached its active=0A= state, or when the profile's stored and computed CRCs disagree. In=0A= both cases every register still reads back a plausible value, so=0A= nothing about the failure is visible until the measurements come out=0A= wrong.=0A= =0A= - Say what the phase offset getter measures, next to the callback: the=0A= loop's residual error sampled with the loop closed, which is the=0A= quantity the ABI asks for -- not the vendor's open-loop=0A= phase-difference procedure, which would need the digital loop filter=0A= frozen and would leave the PLL undisciplined until something=0A= released it. A netlink read must not do that.=0A= =0A= - Drop fifteen register definitions that have never had a caller.=0A= Eleven describe that open-loop sequence and the PLL restart path,=0A= neither of which the driver performs. The other four -- the PLL page=0A= macro and the three DIVN2 fields -- had no user in any patch of the=0A= split, so there was no honest patch to introduce them in. Each will=0A= come back with its first user.=0A= =0A= - Binding: put the example VCO frequency inside a band. 6251500000 sat=0A= in the gap between the device's two bands, which the property's own=0A= description rules out; it is now 6900000000, which a shipping=0A= profile on our SiT95316 board runs. This is the only change to the=0A= binding since v6 -- the property and its description are unchanged=0A= -- so Krzysztof's Reviewed-by is carried across it.=0A= =0A= The AI review's use-after-free report on the pin properties remains a=0A= false positive: dpll_pin_alloc() calls dpll_pin_prop_dup(), which copies=0A= freq_supported with kmemdup() and the labels with kstrdup(), so the core=0A= owns its copies and the driver has to free its own.=0A= =0A= Ali Rouhi (2):=0A= dt-bindings: vendor-prefixes: add SiTime Corporation=0A= dt-bindings: dpll: add SiTime SiT95316 clock generator=0A= =0A= Oleg Zadorozhnyi (13):=0A= dpll: add basic SiTime SiT9531x support=0A= dpll: sit9531x: read DPLL types and pin properties from system=0A= firmware=0A= dpll: sit9531x: register DPLL devices and pins=0A= dpll: sit9531x: implement input pin state on a DPLL=0A= dpll: sit9531x: add support to get and set priority on input pins=0A= dpll: sit9531x: add support to get and set frequency on pins=0A= dpll: sit9531x: implement output pin state on a DPLL=0A= dpll: sit9531x: add support to adjust output phase=0A= dpll: sit9531x: add support to get and set esync on pins=0A= dpll: sit9531x: add support to get phase offset on the connected input=0A= pin=0A= dpll: sit9531x: add support to get fractional frequency offset=0A= dpll: sit9531x: model the inter-PLL sync net as a pair of pins=0A= dpll: sit9531x: allow the device tree to override two board facts=0A= =0A= .../bindings/dpll/sitime,sit95316.yaml | 171 +=0A= .../devicetree/bindings/vendor-prefixes.yaml | 2 +=0A= MAINTAINERS | 7 +=0A= drivers/dpll/Kconfig | 2 +=0A= drivers/dpll/Makefile | 1 +=0A= drivers/dpll/sit9531x/Kconfig | 17 +=0A= drivers/dpll/sit9531x/Makefile | 4 +=0A= drivers/dpll/sit9531x/core.c | 3317 +++++++++++++++++=0A= drivers/dpll/sit9531x/core.h | 381 ++=0A= drivers/dpll/sit9531x/dpll.c | 1335 +++++++=0A= drivers/dpll/sit9531x/dpll.h | 69 +=0A= drivers/dpll/sit9531x/prop.c | 406 ++=0A= drivers/dpll/sit9531x/prop.h | 39 +=0A= drivers/dpll/sit9531x/regs.h | 377 ++=0A= 14 files changed, 6128 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= create mode 100644 drivers/dpll/sit9531x/Kconfig=0A= create mode 100644 drivers/dpll/sit9531x/Makefile=0A= create mode 100644 drivers/dpll/sit9531x/core.c=0A= create mode 100644 drivers/dpll/sit9531x/core.h=0A= create mode 100644 drivers/dpll/sit9531x/dpll.c=0A= create mode 100644 drivers/dpll/sit9531x/dpll.h=0A= create mode 100644 drivers/dpll/sit9531x/prop.c=0A= create mode 100644 drivers/dpll/sit9531x/prop.h=0A= create mode 100644 drivers/dpll/sit9531x/regs.h=0A= =0A= =0A= base-commit: d0ec95a8a4e79f2fd6063fc8932415db8c227689=0A= -- =0A= 2.43.0=0A= =0A=