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From: Oleg Zadorozhnyi =0A= =0A= Embedded sync marks a one-pulse-per-second boundary inside a higher-rate=0A= output by widening one pulse. On this device that is the same divider=0A= programming as a frequency change plus the per-output pulse control, so=0A= enabling it sets the output to 1 Hz and disabling it restores the=0A= requested rate.=0A= =0A= Only outputs the firmware describes as esync-controllable offer it; on the= =0A= rest the operations are refused rather than silently reprogramming an=0A= output whose board wiring does not expect it. The pulse width is fixed at= =0A= half the period, which is what the device produces, and the core is told=0A= the supported range rather than left to guess.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Assisted-by: Claude:claude-4-opus [chat]=0A= Signed-off-by: Ali Rouhi =0A= ---=0A= drivers/dpll/sit9531x/core.c | 51 +++++++++++++++++++=0A= drivers/dpll/sit9531x/dpll.c | 99 ++++++++++++++++++++++++++++++++++++=0A= drivers/dpll/sit9531x/regs.h | 7 +++=0A= 3 files changed, 157 insertions(+)=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c=0A= index be033d7cfe7c..c93578f3b750 100644=0A= --- a/drivers/dpll/sit9531x/core.c=0A= +++ b/drivers/dpll/sit9531x/core.c=0A= @@ -1535,6 +1535,57 @@ int sit9531x_clear_notifications(struct sit9531x_dev= *sitdev)=0A= return 0;=0A= }=0A= =0A= +/*=0A= + * sit9531x_output_pulse_ctrl_set - program per-output PULSE_CTRL byte=0A= + * @out_idx: logical output index (translated to chip slot internally)=0A= + * @pulse_ctrl: 8-bit PULSE_CTRL value (PROG0)=0A= + *=0A= + * Writes ODRn_PROG0 on the output page (Page 3 for slots 0..5,=0A= + * Page 4 for slots 6..11) at offset 0x1B + 16 * (slot % 6).=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_output_pulse_ctrl_set(struct sit9531x_dev *sitdev,=0A= + u8 out_idx, u8 pulse_ctrl)=0A= +{=0A= + const struct sit9531x_chip_info *info =3D sitdev->info;=0A= + u8 slot, page, reg;=0A= + int rc, ret;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (out_idx >=3D info->num_outputs)=0A= + return -EINVAL;=0A= +=0A= + slot =3D info->clkout_map[out_idx];=0A= + page =3D (slot > SIT9531X_PAGE_OUTSYS0_SLOT_MAX) ?=0A= + SIT9531X_PAGE_OUTSYS1 : SIT9531X_PAGE_OUTSYS0;=0A= + reg =3D SIT9531X_OUT_PROG0_BASE +=0A= + SIT9531X_OUT_PRG_SLOT_STRIDE * (slot % 6);=0A= +=0A= + /*=0A= + * PROG0 lives in the output system, so like the DIVO and=0A= + * PRG_RST_DELAY writes it only takes effect inside the PRG_CMD=0A= + * programming state committed to the NVM shadow.=0A= + */=0A= + rc =3D sit9531x_prg_enter(sitdev);=0A= + if (rc)=0A= + return rc;=0A= +=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG(page, reg), pulse_ctrl);=0A= +=0A= + /*=0A= + * Always leave the PRG_CMD state via prg_commit(), even if the write=0A= + * failed, so the output loops are re-locked rather than stranded=0A= + * unlocked; keep the first error.=0A= + */=0A= + ret =3D sit9531x_prg_commit(sitdev);=0A= + if (ret && !rc)=0A= + rc =3D ret;=0A= +=0A= + return rc;=0A= +}=0A= +=0A= /*=0A= * sit9531x_ref_state_fetch - read input reference status from hardware=0A= * @index: logical input index=0A= diff --git a/drivers/dpll/sit9531x/dpll.c b/drivers/dpll/sit9531x/dpll.c=0A= index c07fb2256510..76d7d7d21d3d 100644=0A= --- a/drivers/dpll/sit9531x/dpll.c=0A= +++ b/drivers/dpll/sit9531x/dpll.c=0A= @@ -25,6 +25,17 @@=0A= #define SIT9531X_ESYNC_FREQ_10MHZ 10000000ULL=0A= #define SIT9531X_ESYNC_PULSE_DEFAULT 50=0A= =0A= +static const struct dpll_pin_frequency sit9531x_esync_ranges[] =3D {=0A= + DPLL_PIN_FREQUENCY(0),=0A= + DPLL_PIN_FREQUENCY(SIT9531X_ESYNC_FREQ_10MHZ),=0A= +};=0A= +=0A= +static inline bool=0A= +sit9531x_dpll_esync_pin_supported(const struct sit9531x_dpll_pin *dpin)=0A= +{=0A= + return dpin->esync_control;=0A= +}=0A= +=0A= static inline bool sit9531x_dpll_is_input_pin(const struct sit9531x_dpll_p= in *pin)=0A= {=0A= return pin->dir =3D=3D DPLL_PIN_DIRECTION_INPUT;=0A= @@ -785,6 +796,92 @@ sit9531x_dpll_output_pin_phase_adjust_set(const struct= dpll_pin *pin,=0A= return 0;=0A= }=0A= =0A= +static int=0A= +sit9531x_dpll_output_pin_esync_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + struct dpll_pin_esync *esync,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll_pin *dpin =3D pin_priv;=0A= +=0A= + if (!sit9531x_dpll_esync_pin_supported(dpin))=0A= + return -EOPNOTSUPP;=0A= +=0A= + esync->range =3D sit9531x_esync_ranges;=0A= + esync->range_num =3D ARRAY_SIZE(sit9531x_esync_ranges);=0A= + esync->pulse =3D SIT9531X_ESYNC_PULSE_DEFAULT;=0A= + esync->freq =3D dpin->esync_freq;=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +static int=0A= +sit9531x_dpll_output_pin_esync_set(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + u64 freq,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll_pin *dpin =3D pin_priv;=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + u8 actual_pll;=0A= + int rc;=0A= +=0A= + if (!sit9531x_dpll_esync_pin_supported(dpin)) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "Embedded sync not enabled for this pin");=0A= + return -EOPNOTSUPP;=0A= + }=0A= +=0A= + actual_pll =3D sitdev->out[dpin->id].pll_idx;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + /*=0A= + * This output is a dedicated embedded-sync pin.=0A= + * Treat freq=3D0 as a request to disable the entire output.=0A= + */=0A= + if (!freq) {=0A= + rc =3D sit9531x_output_disable(sitdev, dpin->id);=0A= + if (!rc)=0A= + dpin->esync_freq =3D 0;=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= + return rc;=0A= + }=0A= +=0A= + if (freq !=3D SIT9531X_ESYNC_FREQ_10MHZ) {=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= + NL_SET_ERR_MSG(extack,=0A= + "Only 10 MHz esync frequency is supported");=0A= + return -EINVAL;=0A= + }=0A= +=0A= + rc =3D sit9531x_output_freq_set(sitdev, dpin->id, actual_pll,=0A= + SIT9531X_ESYNC_FREQ_10MHZ);=0A= + /*=0A= + * Program the pulse generator (PROG0 PULSE_CTRL) so the embedded-sync=0A= + * pulse is actually emitted; without it the output carries the clock=0A= + * but no esync marker. SIT9531X_ESYNC_PULSE_DEFAULT is the same duty=0A= + * the esync_get callback advertises.=0A= + */=0A= + if (!rc)=0A= + rc =3D sit9531x_output_pulse_ctrl_set(sitdev, dpin->id,=0A= + SIT9531X_ESYNC_PULSE_DEFAULT);=0A= + if (!rc)=0A= + rc =3D sit9531x_output_enable(sitdev, dpin->id);=0A= +=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + if (!rc)=0A= + dpin->esync_freq =3D SIT9531X_ESYNC_FREQ_10MHZ;=0A= +=0A= + return rc;=0A= +}=0A= +=0A= static const struct dpll_pin_ops sit9531x_dpll_output_pin_ops =3D {=0A= .direction_get =3D sit9531x_dpll_output_pin_direction_get,=0A= .frequency_get =3D sit9531x_dpll_output_pin_frequency_get,=0A= @@ -793,6 +890,8 @@ static const struct dpll_pin_ops sit9531x_dpll_output_p= in_ops =3D {=0A= .state_on_dpll_set =3D sit9531x_dpll_output_pin_state_on_dpll_set,=0A= .phase_adjust_get =3D sit9531x_dpll_output_pin_phase_adjust_get,=0A= .phase_adjust_set =3D sit9531x_dpll_output_pin_phase_adjust_set,=0A= + .esync_get =3D sit9531x_dpll_output_pin_esync_get,=0A= + .esync_set =3D sit9531x_dpll_output_pin_esync_set,=0A= };=0A= =0A= const struct dpll_pin_ops *=0A= diff --git a/drivers/dpll/sit9531x/regs.h b/drivers/dpll/sit9531x/regs.h=0A= index 91d33abd15c3..251c98dc7cbe 100644=0A= --- a/drivers/dpll/sit9531x/regs.h=0A= +++ b/drivers/dpll/sit9531x/regs.h=0A= @@ -215,6 +215,13 @@=0A= #define SIT9531X_OUT_PRG_FINE_MAX 7 /* 3-bit field */=0A= #define SIT9531X_OUT_PRG_COARSE_BITS 34=0A= =0A= +/*=0A= + * Per-output pulse-count control byte used in SYSREF / SYNCB modes.=0A= + * Slot N within a page sits at 0x1B + 16 * (slot % 6). Same page=0A= + * mapping as PRG_RST_DELAY: slots 0-5 on Page 3, slots 6-11 on Page 4.=0A= + */=0A= +#define SIT9531X_OUT_PROG0_BASE 0x1B=0A= +=0A= /*=0A= * On-demand phase-flush fired from a register rather than a GPIO pin.=0A= * DIVO_PHASE_SEL_REG selects the in-register trigger source and=0A= -- =0A= 2.43.0=0A= =0A=