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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v12 3/5] net: dsa: motorcomm: Split SMI module Date: Thu, 3 Sep 2026 11:16:24 +0800 Message-ID: <20260903031630.356840-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260903031630.356840-1-mmyangfl@gmail.com> References: <20260903031630.356840-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit SMI operations are going to be used across different modules. Minor changes are applied to fix build errors. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/motorcomm/Makefile | 1 + drivers/net/dsa/motorcomm/chip.c | 207 +---------------------------- drivers/net/dsa/motorcomm/smi.c | 180 +++++++++++++++++++++++++ drivers/net/dsa/motorcomm/smi.h | 61 +++++++++ 4 files changed, 243 insertions(+), 206 deletions(-) create mode 100644 drivers/net/dsa/motorcomm/smi.c create mode 100644 drivers/net/dsa/motorcomm/smi.h diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm/Makefile index bf99feb4c454..9fa24929007c 100644 --- a/drivers/net/dsa/motorcomm/Makefile +++ b/drivers/net/dsa/motorcomm/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_YT921X) += yt921x.o yt921x-objs := chip.o +yt921x-objs += smi.o diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/chip.c index 019b3a2d5d97..6dee25b6754a 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -27,6 +26,7 @@ #include #include "chip.h" +#include "smi.h" struct yt921x_mib_desc { unsigned int size; @@ -155,9 +155,6 @@ static const struct yt921x_info yt921x_infos[] = { #define YT921X_VID_UNWARE 4095 -#define YT921X_POLL_SLEEP_US 10000 -#define YT921X_POLL_TIMEOUT_US 100000 - /* The interval should be small enough to avoid overflow of 32bit MIBs. * * Until we can read MIBs from stats64 call directly (i.e. sleep @@ -196,208 +193,6 @@ static u32 ethaddr_lo2_to_u32(const unsigned char *addr) return (addr[4] << 8) | addr[5]; } -static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) -{ - lockdep_assert_held_once(&priv->reg_lock); - - return priv->reg_ops->read(priv->reg_ctx, reg, valp); -} - -static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) -{ - lockdep_assert_held_once(&priv->reg_lock); - - return priv->reg_ops->write(priv->reg_ctx, reg, val); -} - -static int -yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) -{ - u32 val; - int res; - int ret; - - ret = read_poll_timeout(yt921x_reg_read, res, - res || (val & mask) == *valp, - YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, - false, priv, reg, &val); - if (ret) - return ret; - if (res) - return res; - - *valp = val; - return 0; -} - -static int -yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) -{ - int res; - u32 v; - u32 u; - - res = yt921x_reg_read(priv, reg, &v); - if (res) - return res; - - u = v; - u &= ~mask; - u |= val; - if (u == v) - return 0; - - return yt921x_reg_write(priv, reg, u); -} - -static int yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) -{ - return yt921x_reg_update_bits(priv, reg, 0, mask); -} - -static int yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) -{ - return yt921x_reg_update_bits(priv, reg, mask, 0); -} - -static int -yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) -{ - return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); -} - -/* Some multi-word registers, like VLANn_CTRL, should be treated as a single - * long register. More specifically, writes to parts of its words won't become - * visible, until the last word is written. - * - * Here we require full read and write operations over these registers to - * eliminate potential issues, although partial reads/writes are also possible. - */ - -static void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 val) -{ - *lo &= ~lower_32_bits(mask); - *hi &= ~upper_32_bits(mask); - *lo |= lower_32_bits(val); - *hi |= upper_32_bits(val); -} - -static int -yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i = 0; i < num_regs; i++) { - res = yt921x_reg_read(priv, reg + 4 * i, &vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i = 0; i < num_regs; i++) { - res = yt921x_reg_write(priv, reg + 4 * i, vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - const u32 *vals, unsigned int num_regs) -{ - bool changed = false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res = yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i = 0; i < num_regs; i++) { - u32 u = vs[i]; - - u &= ~masks[i]; - u |= vals[i]; - if (u != vs[i]) - changed = true; - - vs[i] = u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - unsigned int num_regs) -{ - bool changed = false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res = yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i = 0; i < num_regs; i++) { - u32 u = vs[i]; - - u &= ~masks[i]; - if (u != vs[i]) - changed = true; - - vs[i] = u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 2); -} - -static int -yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - const u32 *vals) -{ - return yt921x_regs_update_bits(priv, reg, masks, vals, 2); -} - -static int -yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks) -{ - return yt921x_regs_clear_bits(priv, reg, masks, 2); -} - -static int -yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 3); -} - static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) { struct yt921x_reg_mdio *mdio = context; diff --git a/drivers/net/dsa/motorcomm/smi.c b/drivers/net/dsa/motorcomm/smi.c new file mode 100644 index 000000000000..bf3adfd64165 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 David Yang + */ + +#include + +#include "chip.h" +#include "smi.h" + +#define YT921X_POLL_SLEEP_US 10000 +#define YT921X_POLL_TIMEOUT_US 100000 + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->read(priv->reg_ctx, reg, valp); +} + +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->write(priv->reg_ctx, reg, val); +} + +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) +{ + u32 val; + int res; + int ret; + + ret = read_poll_timeout(yt921x_reg_read, res, + res || (val & mask) == *valp, + YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, + false, priv, reg, &val); + if (ret) + return ret; + if (res) + return res; + + *valp = val; + return 0; +} + +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) +{ + int res; + u32 v; + u32 u; + + res = yt921x_reg_read(priv, reg, &v); + if (res) + return res; + + u = v; + u &= ~mask; + u |= val; + if (u == v) + return 0; + + return yt921x_reg_write(priv, reg, u); +} + +static int +yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i = 0; i < num_regs; i++) { + res = yt921x_reg_read(priv, reg + 4 * i, &vals[i]); + if (res) + return res; + } + + return 0; +} + +static int +yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i = 0; i < num_regs; i++) { + res = yt921x_reg_write(priv, reg + 4 * i, vals[i]); + if (res) + return res; + } + + return 0; +} + +static int +yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + const u32 *vals, unsigned int num_regs) +{ + bool changed = false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); + + res = yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i = 0; i < num_regs; i++) { + u32 u = vs[i]; + + u &= ~masks[i]; + u |= vals[i]; + if (u != vs[i]) + changed = true; + + vs[i] = u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} + +static int +yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + unsigned int num_regs) +{ + bool changed = false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); + + res = yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i = 0; i < num_regs; i++) { + u32 u = vs[i]; + + u &= ~masks[i]; + if (u != vs[i]) + changed = true; + + vs[i] = u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} + +int +yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 2); +} + +int +yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + const u32 *vals) +{ + return yt921x_regs_update_bits(priv, reg, masks, vals, 2); +} + +int +yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks) +{ + return yt921x_regs_clear_bits(priv, reg, masks, 2); +} + +int +yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 3); +} diff --git a/drivers/net/dsa/motorcomm/smi.h b/drivers/net/dsa/motorcomm/smi.h new file mode 100644 index 000000000000..212e20f71d80 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2026 David Yang + */ + +#ifndef _YT_SMI_H +#define _YT_SMI_H + +#include +#include + +struct yt921x_priv; + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp); +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val); +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp); +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, + u32 val); + +static inline int +yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, 0, mask); +} + +static inline int +yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, mask, 0); +} + +static inline int +yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) +{ + return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); +} + +/* Some multi-word registers, like VLANn_CTRL, should be treated as a single + * long register. More specifically, writes to parts of its words won't become + * visible, until the last word is written. + * + * Here we require full read and write operations over these registers to + * eliminate potential issues, although partial reads/writes are also possible. + */ + +static inline void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 val) +{ + *lo &= ~lower_32_bits(mask); + *hi &= ~upper_32_bits(mask); + *lo |= lower_32_bits(val); + *hi |= upper_32_bits(val); +} + +int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals); +int yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, + const u32 *masks, const u32 *vals); +int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, + const u32 *masks); +int yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals); + +#endif -- 2.53.0