From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A4DA4446E3; Thu, 3 Sep 2026 07:29:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420600; cv=none; b=rfSDOJXaQYHL228nZgfsJMEEEw7XcZz2WET2mKfmF5DpDRiMqVJJpo9WgCAaWtQtmyqBi7AfeCm612BJf5B2XeCZvrXGcIgacziHDL1pr+fcBZRFSilW1fPnbibWTzn/MSnz9KYS2EbM0lJOSNCMIZPDEFxLoJUPe+HT0kef0CA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788420600; c=relaxed/simple; bh=Rty2NtKQP8y+KjwSk/Bvb9SYsgBKslmoaYjreagYYP0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T1USBebF5TE5KhPQU4hPtbLlOuUvTDLLmr099Dx9O5Gk4AjFGEAqYcpjlQ8g3+b8RYfyBcIF7vMfBW1Ryq8cwUCRsdDjYFuLio6aToj4sBDNfRTd0iQ6UVe+eR8bujBGfboxeAKQLAgmYpjESnoMvsh5pPmYIjjJyxOF0HkeA1A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=W38kw8fe; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="W38kw8fe" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6837StFcA3295546, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1788420535; bh=5jxBQ5lAZdNFYIj+oj2mBMwePFOO853wUxi5efmd17U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=W38kw8feyutWX7v8YmaAhlzThddkAdfjN56VUNiuVO6Aq+Bbu2+ap7ia73vCNWsEM Cm09xQ0smr7JuLujfdeEi0QPFomUQfgGtZPOpLSe6l2cUduWy4mTr7veWb0Z2NA9LM kusGbRkSkjYv10c2GH3UuHizdXciyCOo2JssQPtOpZqo7ascSq6WWj+4hS6AEcxGFc xhX/nD4OTF4fX9FsyGcAG/qba6Pr1Am0VrUxEtbiEAiPGp7q3IjfT8IyIZuKlJElhf H57jk+jDWDlbdd5ECU/DtVDdnH0ecvAcEpiHrV9Evc2tzUBrwoQ9AbYkxfgyOwTX5H ZcfOz6gxyzLLg== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6837StFcA3295546 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Sep 2026 15:28:55 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Thu, 3 Sep 2026 15:28:54 +0800 Received: from fc44.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Thu, 3 Sep 2026 15:28:54 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , , Subject: [PATCH net-next v2 6/8] r8152: add TGPHY access support Date: Thu, 3 Sep 2026 15:28:50 +0800 Message-ID: <20260903072852.58695-7-nic_swsd@realtek.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260903072852.58695-1-nic_swsd@realtek.com> References: <20260903072852.58695-1-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain RTL8157 and RTL8159 support a TGPHY interface via USB_TGPHY_CMD/ADDR/DATA, which allows reading/writing PHY registers without changing the OCP base address at 0xe86c. Add r8157_phy_read/phy_write implementing this path, and add phy_read/phy_write function pointers to struct rtl_ops to dispatch the correct access method per chip. Signed-off-by: Chih Kai Hsu --- drivers/net/usb/r8152.c | 94 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 1bf465b1cacb3..b4253b00aa64e 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -162,6 +162,9 @@ #define USB_ADV_ADDR 0xd5d6 #define USB_ADV_DATA 0xd5d8 #define USB_ADV_CMD 0xd5dc +#define USB_TGPHY_ADDR 0xd630 +#define USB_TGPHY_DATA 0xd632 +#define USB_TGPHY_CMD 0xd634 #define USB_UPS_CTRL 0xd800 #define USB_POWER_CUT 0xd80a #define USB_MISC_0 0xd81a @@ -511,6 +514,10 @@ #define ADV_CMD_WR BIT(1) #define ADV_CMD_IP BIT(2) +/* USB_TGPHY_CMD */ +#define TGPHY_CMD_BUSY BIT(0) +#define TGPHY_CMD_WR BIT(1) + /* USB_UPS_CTRL */ #define POWER_CUT 0x0100 @@ -960,6 +967,8 @@ struct r8152 { void (*hw_phy_cfg)(struct r8152 *tp); void (*autosuspend_en)(struct r8152 *tp, bool enable); void (*change_mtu)(struct r8152 *tp); + u16 (*phy_read)(struct r8152 *tp, u16 addr); + void (*phy_write)(struct r8152 *tp, u16 addr, u16 data); } rtl_ops; struct ups_info { @@ -1666,7 +1675,7 @@ static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); } -static u16 ocp_reg_read(struct r8152 *tp, u16 addr) +static u16 r8152_phy_read(struct r8152 *tp, u16 addr) { u16 ocp_base, ocp_index; @@ -1680,7 +1689,7 @@ static u16 ocp_reg_read(struct r8152 *tp, u16 addr) return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); } -static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) +static void r8152_phy_write(struct r8152 *tp, u16 addr, u16 data) { u16 ocp_base, ocp_index; @@ -1694,6 +1703,16 @@ static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); } +static u16 ocp_reg_read(struct r8152 *tp, u16 addr) +{ + return tp->rtl_ops.phy_read(tp, addr); +} + +static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) +{ + tp->rtl_ops.phy_write(tp, addr, data); +} + static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) { ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); @@ -2030,6 +2049,61 @@ static int r8152_mdio_test_and_clr_bit(struct r8152 *tp, u16 addr, u16 clear) return data & clear; } +static int wait_tgphy_cmd_ready(struct r8152 *tp) +{ + u16 ocp_data; + + return poll_timeout_us(ocp_data = ocp_read_word(tp, MCU_TYPE_USB, + USB_TGPHY_CMD), + !(ocp_data & TGPHY_CMD_BUSY), 2000, 20000, + false); +} + +static int rtl_tgphy_access(struct r8152 *tp, u16 addr, u16 *data, bool write) +{ + u16 cmd = 0; + int ret; + + ret = wait_tgphy_cmd_ready(tp); + if (ret < 0) + goto out; + + if (write) { + cmd |= TGPHY_CMD_WR; + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_DATA, *data); + } + + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_ADDR, addr); + + cmd |= TGPHY_CMD_BUSY; + ocp_write_word(tp, MCU_TYPE_USB, USB_TGPHY_CMD, cmd); + + if (!write) { + ret = wait_tgphy_cmd_ready(tp); + if (ret < 0) + goto out; + + *data = ocp_read_word(tp, MCU_TYPE_USB, USB_TGPHY_DATA); + } + +out: + return ret; +} + +static u16 r8157_phy_read(struct r8152 *tp, u16 addr) +{ + u16 data = 0; + + rtl_tgphy_access(tp, addr, &data, false); + + return data; +} + +static void r8157_phy_write(struct r8152 *tp, u16 addr, u16 data) +{ + rtl_tgphy_access(tp, addr, &data, true); +} + static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); @@ -10281,6 +10355,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->in_nway = rtl8152_in_nway; ops->hw_phy_cfg = r8152b_hw_phy_cfg; ops->autosuspend_en = rtl_runtime_suspend_enable; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; tp->rx_buf_sz = 16 * 1024; tp->eee_en = true; tp->eee_adv = MDIO_EEE_100TX; @@ -10303,6 +10379,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8153_hw_phy_cfg; ops->autosuspend_en = rtl8153_runtime_enable; ops->change_mtu = rtl8153_change_mtu; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; if (tp->udev->speed < USB_SPEED_SUPER) tp->rx_buf_sz = 16 * 1024; else @@ -10326,6 +10404,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8153b_hw_phy_cfg; ops->autosuspend_en = rtl8153b_runtime_enable; ops->change_mtu = rtl8153_change_mtu; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; tp->rx_buf_sz = 32 * 1024; tp->eee_en = true; tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; @@ -10350,6 +10430,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8156_hw_phy_cfg; ops->autosuspend_en = rtl8156_runtime_enable; ops->change_mtu = rtl8156_change_mtu; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; tp->rx_buf_sz = 48 * 1024; tp->support_2500full = 1; r8152_desc_init(tp); @@ -10375,6 +10457,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8156b_hw_phy_cfg; ops->autosuspend_en = rtl8156_runtime_enable; ops->change_mtu = rtl8156_change_mtu; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; tp->rx_buf_sz = 48 * 1024; r8152_desc_init(tp); break; @@ -10392,6 +10476,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8153c_hw_phy_cfg; ops->autosuspend_en = rtl8153c_runtime_enable; ops->change_mtu = rtl8153c_change_mtu; + ops->phy_read = r8152_phy_read; + ops->phy_write = r8152_phy_write; tp->rx_buf_sz = 32 * 1024; tp->eee_en = true; tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; @@ -10414,6 +10500,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8157_hw_phy_cfg; ops->autosuspend_en = rtl8157_runtime_enable; ops->change_mtu = rtl8157_change_mtu; + ops->phy_read = r8157_phy_read; + ops->phy_write = r8157_phy_write; tp->rx_buf_sz = 32 * 1024; tp->support_2500full = 1; tp->support_5000full = 1; @@ -10437,6 +10525,8 @@ static int rtl_ops_init(struct r8152 *tp) ops->hw_phy_cfg = r8159_hw_phy_cfg; ops->autosuspend_en = rtl8157_runtime_enable; ops->change_mtu = rtl8157_change_mtu; + ops->phy_read = r8157_phy_read; + ops->phy_write = r8157_phy_write; tp->rx_buf_sz = 48 * 1024; tp->support_2500full = 1; tp->support_5000full = 1; -- 2.34.1