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Thu, 3 Sep 2026 01:53:59 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Alexei Starovoitov , Allison Henderson , Antonio Quartulli , Anubhav Singh , Bobby Eshleman , Boris Pismenny , , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Borkmann , Daniel Zahka , David Wei , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jesper Dangaard Brouer , "Jianbo Liu" , John Fastabend , "Kees Cook" , Lama Kayal , Leon Romanovsky , open list , , , Mark Bloch , "Matthieu Baerts (NGI0)" , Patrisious Haddad , Petr Machata , "Raed Salem" , Rahul Rameshbabu , "Richard Gobert" , Saeed Mahameed , "Shuah Khan" , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan , Willem de Bruijn , Willem de Bruijn Subject: [PATCH net-next V3 06/15] net/mlx5e: ipsec: Move RX marker from ft_metadata to flow_tag Date: Thu, 3 Sep 2026 11:52:06 +0300 Message-ID: <20260903085215.3691657-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260903085215.3691657-1-tariqt@nvidia.com> References: <20260903085215.3691657-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A804:EE_|SJ1PR12MB6124:EE_ X-MS-Office365-Filtering-Correlation-Id: a28f014a-13ca-4792-6053-08df0998f728 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|7416014|376014|18002099003|6133799003|22082099003|3023799007|56012099006|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: IC5N9Hp/SbFlcVEHmzYiQNGPsdRQqkwf2YqD8/P13zYQzUIgZ2bTKpVIYiTJSyW4fJMCQGkvCpVg4LjZB6Kz2SEjbHN5jbAqyf6Ckhvc6qcrgF9d+7jF6ipAJG84/qwALOPfMa7aStR4nICn0K8gZVlvmquJs6bfpIGdjUi83RIcnbBsAOGIyZmwUZAErabMpX5rNX87r/OQKWzmAt4ibq8I+50lSz5gCXlCApEMLiQ33htpZVhMa0q6UwRtfX+tOqstF/me/PrDDySI2AVAeMO9bPk/yZWkKX3YAehxW/i85rz2suLJqR4xTvo7RXpQ0bRCGJUIuxN6ejbIEQRVAXTghlNxYMW+gE+Hp3LjsjxaImatBQodaulP8j/OUk4+djuWGYf0x6PlnR2+0ldKIraU/az/Im7sMsBHg9uTJia0KsnRIsmESzCsHOVopdv85d3AB6LWxAL+CPlUs5DqNTCn3yHfLQVgzTbiqDZCFSVGmxEL5CVE9cwjFLqljTTUR5sFcb6VcedAyjlB5eW2GMtKi3Oioq63azmT5phaPfAzgx9jw/AAaJ5m8k08/evLqVJGWvaPSZUc66cqd4qFyJofWrFN7A4NvdiE5NuIN636ydOn6Z+ujsb15P+XOHNwIK/mago2T6EG1YtlmgMKUxsL0sORCE8at9VvnpyAebpr+GGOPrWMCdDGvDxFeQn0Tziz7lZq4IWbfIEfWbPz0Q== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(23010399003)(7416014)(376014)(18002099003)(6133799003)(22082099003)(3023799007)(56012099006)(10067099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WqAADZLuFgVPwoM40E6xmYbjhGrDeKRrzm4DBeSb+SVxjnhVCJxayQp93u6s6WBOK0Lz2qQFv3C0Yp2jL5y42qrje0z/ODcdiW9Z2egFHHBczXk7YS46kyL1KTXprOoxtyD1RBqe24yjtG2VcjzPEt7OUxSBfTZM3iNUMw9y1uVHqK2kWQYJxgrjRWGX4QeR1Voe9gH4ReKPR9We7pkl+Ofqu1+YTbpQjmOU6Z6GgcJOKe3wOYt/MjR/9PMBF+Xt+fwFR2TA3tY8WNCbjJls3EibRZrqPmqlIe0TaiyXhuqeOfezrNgG+aj0kV2fwH/XOeMIt4mmHs2nHF0eDpNhaQQsowrO45g5PTo9/LS90gXVzk62ij3vcohYSTbzWbu8XzfZbRa89X0xY9vn92vJgntvP8Gtb19KkXf5KaEcp3V9p90WwECeRrBILg0805f/ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2026 08:54:29.4714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a28f014a-13ca-4792-6053-08df0998f728 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A804.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6124 From: Cosmin Ratiu IPsec used BIT(31) in cqe.ft_metadata as a marker for ingress IPsec-decrypted packets. This will conflict with PSP which stores SPI in ft_metadata - an SPI with bit 31 set would falsely trigger mlx5_ipsec_is_rx_flow(). Define a new marker for IPsec in flow_tag and use it in steering rules. The obj_id stays in ft_metadata bits[23:0]. Remove the unused MARKER and SYNDROM (sic) macros. This is only done for IPsec NIC RX flows. The esw path uses a different mechanism and is unaffected: RX handling in mlx5e_rep_tc_receive() makes use of a few bits in ft_metadata to detect and hand off IPsec packets to mlx5e_ipsec_offload_handle_rx_skb(). An additional complication is that mlx5e_cqe_regb_chain() used the high order bits of ft_metadata to differentiate between TC chains and protocol markers. With the IPSec marker moving to flow_tag, this would falsely trigger mlx5e_cqe_regb_chain() to believe the chain is set, when in fact, ft_metadata is something completely different. Solve that by requiring that the new flow_tag proto is NONE, since only those packets can carry a chain id in ft_metadata. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_accel/flow_tag.h | 4 +++- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c | 11 +++++++++-- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 8 ++++---- drivers/net/ethernet/mellanox/mlx5/core/en_tc.h | 7 +++++-- 4 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h index b6fcd4b63031..cf30096d6a37 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h @@ -14,8 +14,9 @@ * * [23:21] = protocol ID (3 bits): * 0 = none (default) + * 1 = IPsec * 3 = PSP (HW decrypted, PSP header present) - * 1,2,4-7 = reserved + * 2,4-7 = reserved * [20:16] = reserved * [15:0] = used by other subsystems (e.g. TC). */ @@ -24,6 +25,7 @@ enum { MLX5E_ACCEL_FLOW_TAG_PROTO_NONE = 0, + MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC = 1, MLX5E_ACCEL_FLOW_TAG_PROTO_PSP = 3, }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index f236672d3a2a..5565c385258c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -5,6 +5,7 @@ #include "en.h" #include "en/fs.h" #include "en_accel/en_accel.h" +#include "en_accel/flow_tag.h" #include "eswitch.h" #include "ipsec.h" #include "fs_core.h" @@ -190,7 +191,7 @@ static void ipsec_rx_rule_add_match_obj(struct mlx5e_ipsec_sa_entry *sa_entry, misc_parameters_2.metadata_reg_c_2); MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_2, - sa_entry->ipsec_obj_id | BIT(31)); + sa_entry->ipsec_obj_id); spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; } @@ -2066,7 +2067,7 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) if (!attrs->drop) { if (rx != ipsec->rx_esw) err = setup_modify_header(ipsec, attrs->type, - sa_entry->ipsec_obj_id | BIT(31), + sa_entry->ipsec_obj_id, XFRM_DEV_OFFLOAD_IN, &flow_act); else err = mlx5_esw_ipsec_rx_setup_modify_header(sa_entry, &flow_act); @@ -2099,6 +2100,12 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_DROP; else flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + if (!attrs->drop && rx != ipsec->rx_esw) { + spec->flow_context.flags |= FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag = + FIELD_PREP(MLX5E_ACCEL_FLOW_TAG_PROTO_MASK, + MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC); + } dest[0].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; dest[0].ft = rx->ft.status; dest[1].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h index 45b0d19e735c..57aabd5e61ec 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h @@ -38,10 +38,9 @@ #include #include "en.h" #include "en/txrx.h" +#include "en_accel/flow_tag.h" -/* Bit31: IPsec marker, Bit30: reserved, Bit29-24: IPsec syndrome, Bit23-0: IPsec obj id */ -#define MLX5_IPSEC_METADATA_MARKER(metadata) ((((metadata) >> 30) & 0x3) == 0x2) -#define MLX5_IPSEC_METADATA_SYNDROM(metadata) (((metadata) >> 24) & GENMASK(5, 0)) +/* IPsec obj id in ft_metadata bits[23:0] */ #define MLX5_IPSEC_METADATA_HANDLE(metadata) ((metadata) & GENMASK(23, 0)) struct mlx5e_accel_tx_ipsec_state { @@ -74,7 +73,8 @@ static inline unsigned int mlx5e_ipsec_tx_ids_len(struct mlx5e_accel_tx_ipsec_st static inline bool mlx5_ipsec_is_rx_flow(struct mlx5_cqe64 *cqe) { - return MLX5_IPSEC_METADATA_MARKER(be32_to_cpu(cqe->ft_metadata)); + return mlx5e_accel_flow_tag_proto(cqe) == + MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC; } static inline bool mlx5e_ipsec_eseg_meta(struct mlx5_wqe_eth_seg *eseg) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h index e1b8cb78369f..53b6043e33d2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h @@ -36,6 +36,7 @@ #include #include "en.h" #include "eswitch.h" +#include "en_accel/flow_tag.h" #include "en/tc_ct.h" #include "en/tc_tun.h" #include "en/tc/int_port.h" @@ -370,11 +371,13 @@ struct mlx5e_tc_table *mlx5e_tc_table_alloc(void); void mlx5e_tc_table_free(struct mlx5e_tc_table *tc); static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe) { - u32 chain, reg_b; + u32 flow_tag, reg_b, chain; + flow_tag = mlx5e_accel_flow_tag_proto(cqe); reg_b = be32_to_cpu(cqe->ft_metadata); - if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS)) + if (flow_tag != MLX5E_ACCEL_FLOW_TAG_PROTO_NONE || + (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))) return false; chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK; -- 2.44.0