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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788812616; l=2805; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=KsLk75r2w7Y7Td996D/f1RY9lIMY3ClaAGPh1T4xOuA=; b=dBBGlbQ+PXRK8wV2RTj9A9/IfrTUGHY9GlnPObuNyviClmSFJez2HMSBuIgjBJYSaU6yfzIKP OhRIpYexXv8CIc9lrWT634bEjV/CIGTmd+QQsDzMWwxUsfQ4OwMfErw X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Authority-Analysis: v=2.4 cv=QNBYgALL c=1 sm=1 tr=0 ts=6a9f1d9d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=8IO8aBILldGQKMPJy6sA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: bPN33LrRQzYT-1MR82wtMJ86Et_fQL3Q X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDIyNCBTYWx0ZWRfX96fmtJoO5WcW ankEL3AGjCqpMJdSUGDmfw1LJb8eww2S4JfOOUu+J6Y3B0XYw7P9pHwbfnvlt84UiK1Hq3J/ydd iz5HnnxY6A7kY+aKl07RP1ULqGpg4is= X-Proofpoint-GUID: bPN33LrRQzYT-1MR82wtMJ86Et_fQL3Q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDIyNCBTYWx0ZWRfXwMLnpjLQmQpU tZ6w+LuQFC8DsmB7v3ar1hbhijsd8/S2ksrzDbZepxDjkHVWBAeXZ6MS+rhkM6kAUX3AjIyOzRC 10wjpEXd4t0oqXkJBQN9u4exZsy1Yh8xuQej8JyQ8aXDxqxgXc6CDaEY2tq6HvimETPb+3dPYuV sa6uDBar4fu8FVvwdyXAHwEWTlv9CitljjtaqjzW1jYC+I9H95pTf3uYbLqrupXxvUvehpSW+w3 fzdIX5U2GPSCl7LC2QT/TyYM1w0LhnttOPkOvbQDK9Ll11VewXkfYFwHmjrtZH8scS/fm2JTo7p nXE+hoNFddbADsQeOJsw1pHg7nN0IWm51rn3oaAhhMljUCqQgPU1MlN9hcRRr1n9Arb/zkfVBim hrxRouws/pmaqwGP2zk0iY6vkpJ+wn4U1Fmx4Xm52JmH4LCH++9zFRUQgUhOyjDwH/AUQtCsDP1 hAEm0JJShQlXWyC5T/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_05,2026-09-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070224 Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys GMAC IP, similar to previous platforms. Register qcom,shikra-ethqos backed by a new shikra_data descriptor that enables the three NOC clocks required for DMA memory access (axi-noc, pcie-tile-axi-noc, stmmaceth) all at 120 MHz, and the 36-bit DMA address width. As part of the NOC clock voting logic, the qcom-ethqos glue driver takes a second enable reference on the "stmmaceth" clock, which is already enabled by the stmmac core. All three clocks in shikra_noc_clks[] must run at 120 MHz for NOC access, and managing "stmmaceth" through the same clk_bulk path keeps the rate-setting and enable/disable together. Signed-off-by: Mohd Ayaan Anwar --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 8871d285941162c72e2a8f79d2eef915d9283796..c474f1e5a043777a52bcbff8a488640f6dbdca30 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -328,6 +328,36 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { }, }; +static const struct ethqos_noc_clk_cfg shikra_noc_clks[] = { + { "axi-noc", 120000000 }, + { "pcie-tile-axi-noc", 120000000 }, + { "stmmaceth", 120000000 }, +}; + +static const struct ethqos_emac_driver_data shikra_data = { + .dma_addr_width = 36, + .has_emac_ge_3 = true, + .noc_clk_cfg = shikra_noc_clks, + .num_noc_clks = ARRAY_SIZE(shikra_noc_clks), + .rgmii_config_loopback_en = false, + .dwmac4_addrs = { + .dma_chan = 0x00008100, + .dma_chan_offset = 0x1000, + .mtl_chan = 0x00008000, + .mtl_chan_offset = 0x1000, + .mtl_ets_ctrl = 0x00008010, + .mtl_ets_ctrl_offset = 0x1000, + .mtl_txq_weight = 0x00008018, + .mtl_txq_weight_offset = 0x1000, + .mtl_send_slp_cred = 0x0000801c, + .mtl_send_slp_cred_offset = 0x1000, + .mtl_high_cred = 0x00008020, + .mtl_high_cred_offset = 0x1000, + .mtl_low_cred = 0x00008024, + .mtl_low_cred_offset = 0x1000, + }, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev = ðqos->pdev->dev; @@ -962,6 +992,7 @@ static const struct of_device_id qcom_ethqos_match[] = { { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, + { .compatible = "qcom,shikra-ethqos", .data = &shikra_data}, { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, { } }; -- 2.34.1