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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Russell King , Alexander Stein , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, donggeunyoo.kernel@gmail.com Subject: [PATCH net] net: phy: dp83867: restore the LED polarity after a soft reset Date: Tue, 8 Sep 2026 20:49:01 +0900 Message-ID: <20260908114901.74637-1-donggeunyoo.kernel@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit dp83867_led_polarity_set() programs the LEDCR2 polarity bit for a DT-configured LED. It runs once, from phy_probe() via of_phy_leds(). Every phy_init_hw() afterwards (phy_attach_direct(), mdio_bus_phy_resume(), and MAC drivers such as fec_main.c) calls .soft_reset first, and dp83867_phy_reset() issues DP83867_SW_RESET, which restores register defaults. config_init does not touch LEDCR2 and the requested value is not cached, so a DT-configured LED polarity is lost from the first attach onward. The soft reset is the only path that clears LEDCR2, and phy_init_hw() always follows it with config_init. Cache the requested bits and reapply them from dp83867_config_init(). aqr_gen1_config_init() recovers from the same reset the same way (61578f679378). Fixes: 447b80a9330e ("net: phy: dp83867: Add support for active-low LEDs") Assisted-by: Claude:claude-fable-5 Signed-off-by: Donggeun Yoo --- The soft-reset regression was flagged by an automated analysis of an earlier posting of the active-high series. Compile-tested and call-chain-traced only; I have no affected hardware. drivers/net/phy/dp83867.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 88255e92b4cd..c9c3b0062cc7 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -196,6 +196,8 @@ struct dp83867_private { bool set_clk_output; u32 clk_output_sel; bool sgmii_ref_clk_en; + u16 led_polarity; + u16 led_polarity_mask; }; static int dp83867_ack_interrupt(struct phy_device *phydev) @@ -896,6 +898,15 @@ static int dp83867_config_init(struct phy_device *phydev) mask, val); } + /* Restore the LED polarity dropped by the soft reset in phy_init_hw() */ + if (dp83867->led_polarity_mask) { + ret = phy_modify(phydev, DP83867_LEDCR2, + dp83867->led_polarity_mask, + dp83867->led_polarity); + if (ret) + return ret; + } + return 0; } @@ -1141,8 +1152,10 @@ static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index, static int dp83867_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes) { + struct dp83867_private *dp83867 = phydev->priv; + u16 mask = DP83867_LED_POLARITY(index); /* Default active high */ - u16 polarity = DP83867_LED_POLARITY(index); + u16 polarity = mask; u32 mode; for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { @@ -1154,8 +1167,11 @@ static int dp83867_led_polarity_set(struct phy_device *phydev, int index, return -EINVAL; } } - return phy_modify(phydev, DP83867_LEDCR2, - DP83867_LED_POLARITY(index), polarity); + + dp83867->led_polarity_mask |= mask; + dp83867->led_polarity = (dp83867->led_polarity & ~mask) | polarity; + + return phy_modify(phydev, DP83867_LEDCR2, mask, polarity); } static unsigned int dp83867_inband_caps(struct phy_device *phydev, -- 2.53.0