From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87007568543; Wed, 9 Sep 2026 13:01:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958880; cv=none; b=cy6ioZGSTNwDIp9/gzETBlC/UTpSYURK+bPItSJPzoWgUTfp0fZK9x1N5PSanRdUARfu417RvrobVbfeO/2Zz9V/lk2mZyA3Rt1jZSSc+QlKeyDzckiHgWDVIR92vJ7n+WfN9WGArIT7mLm6FgyxCZUl8wPanQQWcZAE6YKdLIE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958880; c=relaxed/simple; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Fwf3T4JC2lfiRbYNkV6Kn5xB5oC0T4bSGKrJWRck8+fiSP54Qj4Ro4zwNK+r+E7IUaORa4KAeEMU+vD0XYmjlHkb4dyXtGdj8gW7aA5TnIQAohSQzp/xT5oOIHbptu2ufuAb6Mu1ykpbwFL3kxI2KclQlCCk0O+j+0ssjWMhqxM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PTFl0Xv8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PTFl0Xv8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958878; x=1820494878; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; b=PTFl0Xv88rfW2RFHgvGEhk4+F5A/o2MbG9Jlp5UE07/Y0xoHXxry5etu QuIEMv+v2o43ywcNtUPnjQiidMBQkzXSZsrGUsaeRMXDMsG9SOPm9iQz+ rdYKxP/4HMpfXH6NpGOvVdkDNmiuI6Dffhu1H/zeK3fj+eQeDk88fYr7p 8HHZ+oHlHVxp0qmZJtU9uRgNb1d4yEX8qTAQy5bLPT+xDvV2e8xtYMJrp +NJPHGK6jhTm+2CQOP6M1ayJFX3SOb+JDDnpmr9Oe9HWXSZs1zs6j6lAN oJHvp13KdX/yDEVfnh+qzAHNuFamKhWzkq/4yStZyeYHhJZXO0fukRYBs g==; X-CSE-ConnectionGUID: E/ZtF3FyRom806v0oaXIxg== X-CSE-MsgGUID: WCrG0WACS7iGeteB5+Hh4g== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="230464608" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:01:17 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:01:13 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:15 +0200 Subject: [PATCH net-next v6 13/14] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260909-lan966x-pci-fdma-v6-13-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, + reg = <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; -- 2.34.1