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This series adds a DPLL subsystem driver for the SiTime SiT95316 and=0A= SiT95317 I2C clock generators. Each device integrates four PLLs with=0A= automatic reference selection and on-chip TDC phase-offset measurement,=0A= and is used for synchronization in telecom, networking, and data-center=0A= timing.=0A= =0A= The series contains the device-tree binding, the driver under=0A= drivers/dpll/sit9531x/, and the MAINTAINERS entry.=0A= =0A= v1 https://lore.kernel.org/netdev/20260511211143.19792-1-arouhi@sitime.com/= =0A= v2 https://lore.kernel.org/netdev/20260520191943.73938-1-arouhi@sitime.com/= =0A= v3 https://lore.kernel.org/netdev/20260731180951.65725-1-arouhi@sitime.com/= =0A= v4 https://lore.kernel.org/netdev/20260806232439.27551-1-arouhi@sitime.com/= =0A= v5 https://lore.kernel.org/netdev/20260810230439.22866-1-arouhi@sitime.com/= =0A= v6 https://lore.kernel.org/netdev/20260812175337.18155-1-arouhi@sitime.com/= =0A= v7 https://lore.kernel.org/netdev/20260815221919.64226-1-arouhi@sitime.com/= =0A= v8 https://lore.kernel.org/netdev/20260902214030.20955-1-arouhi@sitime.com/= =0A= =0A= The driver was a single 5.6k-line patch through v7. Vadim and Ivan asked=0A= for it to be split into logical parts, with the first zl3073x series as=0A= the model, so v8 introduced it feature by feature and v9 keeps that=0A= shape:=0A= =0A= 1-2 bindings: vendor prefix, then the device schema=0A= 3 basic support: paged regmap, variant detection, probe=0A= 4 DPLL types and pin properties from system firmware=0A= 5 register the DPLL devices and pins, and keep their state=0A= 6 input pin state on a DPLL, with the pin-state contract=0A= 7 input pin priority=0A= 8 pin frequency, both directions=0A= 9 output pin state (mute)=0A= 10 output phase adjust=0A= 11 esync on outputs=0A= 12 phase offset through the TDC=0A= 13 fractional frequency offset of the selected reference=0A= 14 the inter-PLL sync net as a pair of pins=0A= 15 optional device-tree overrides for two board facts=0A= =0A= The two bindings patches come first, so the driver never matches on a=0A= compatible string before the schema that describes it is in the tree.=0A= =0A= Each of the thirteen driver patches builds and links on its own: no=0A= patch calls something a later patch introduces, so a bisect cannot land=0A= on a tree that fails to compile. For this posting that was re-checked=0A= patch by patch with W=3D1 and with sparse. checkpatch --strict is clean=0A= except for the "does MAINTAINERS need updating?" hint on patches 4 and=0A= 5, which add files under drivers/dpll/sit9531x/ -- patch 3 already=0A= covers that directory with an F: entry.=0A= =0A= On process, and on Paolo's note against v8: the v8 AI review raised 86=0A= comments across the series, and each one now has an individual reply in=0A= its own sub-thread -- fixed, or answered with the reason it is not a=0A= bug. The second half of that guidance is the more useful half, and we=0A= had not been following it. We now run the same review locally before=0A= posting rather than after; v9 has been through it twice over the whole=0A= series, and what it found is folded into the patches below instead of=0A= being left for the bots to raise again. We intend to keep doing this for=0A= any further revision.=0A= =0A= Changes in v9:=0A= =0A= - Put the cost and the constraints in the commit messages, next to the=0A= code they apply to, rather than only in replies on the list. A=0A= priority-table rewrite forces holdover and takes ten to twenty=0A= milliseconds, because the device cannot change one slot in=0A= isolation. Programming an output divider costs about a hundred=0A= milliseconds under the DPLL core's global lock, most of it the=0A= settling time the part requires after the loop-lock command. The=0A= phase flush that follows a divider write realigns every output on=0A= that PLL, not only the one that changed. The clock_id carries the=0A= I2C adapter number in eight bits, so the collision it admits is=0A= stated rather than designed around. The debug window returns the=0A= previous latch, which is why every read of it triggers three times.=0A= The running feedback divider is two taps sampled separately and can=0A= tear; on a locked loop it moves below what the measurement resolves,=0A= and the part offers no way to latch both at once.=0A= =0A= - Never leave the device armed when a sequence fails partway. The=0A= programming state, the debug window, the on-demand phase flush and=0A= forced holdover are each entered by one write and left by another,=0A= and every fallible step in between now exits through the common=0A= path that issues the second write. The first error is the one=0A= returned, so a transient I2C failure can no longer leave the chip=0A= with its loops open, its debug block unlocked, its flush armed or a=0A= PLL parked in holdover.=0A= =0A= - Answer from the device rather than from a cache where the cache can=0A= be wrong. Whether an output is muted now reads both the force bit=0A= and the state bit, and picks the register bank from the pad's own=0A= CMOS enables, so a single-ended pad is no longer interrogated=0A= through the differential bank or the reverse. State that a write may=0A= have invalidated is marked stale and re-read on the next get instead=0A= of being reported from the last poll. Priority-table membership is=0A= asked of the table.=0A= =0A= - Make .mode_set() idempotent. It reads the outer-loop disable bit=0A= before writing it and does nothing when the PLL is already in=0A= automatic mode. Without that, setting the only mode the driver=0A= advertises a second time, followed by one failed latch, would=0A= restore a disable the PLL never had and drop a running loop into=0A= free-run.=0A= =0A= - Park the poll worker and the INTRB interrupt across system suspend=0A= and take a fresh sample on resume. The tick talks to the device over=0A= I2C, and one landing mid-suspend could tear a paged sequence between=0A= the page-selector write and the register access.=0A= =0A= - Check a PLL's VCO frequency against the device's two bands before=0A= using it, so a value that fell in the gap between them cannot reach=0A= the divider arithmetic.=0A= =0A= - Binding: accept clock-frequency as an alternative to the clocks=0A= phandle, for platforms whose firmware does not expose the crystal=0A= through the clock framework; exactly one of the two is now required.=0A= The sitime,pll-fvco description was also rewritten to say why the=0A= property carries no unit suffix: the values exceed 32 bits and so=0A= need an explicit uint64-array type, and the dtschema meta-schema=0A= does not permit a type $ref on a "-hz" property. That was a review=0A= suggestion we tried and dt_binding_check rejected, so the reason is=0A= recorded in the binding itself. The schema changed, so Krzysztof's=0A= Reviewed-by is not carried across it. Patch 1 is unchanged since v8=0A= and keeps Conor's Acked-by.=0A= =0A= One finding from the v8 review is declined rather than fixed, and the=0A= reply on patch 8 gives the argument: a frequency request of 0 Hz is=0A= refused with -EINVAL instead of being treated as a request to stop the=0A= output. Nothing in the ABI says zero means off, and this device already=0A= has a mute control that says so explicitly.=0A= =0A= The use-after-free report on the pin properties remains a false=0A= positive: dpll_pin_alloc() calls dpll_pin_prop_dup(), which copies=0A= freq_supported with kmemdup() and the labels with kstrdup(), so the core=0A= owns its copies and the driver has to free its own.=0A= =0A= The review also turned up one bug that is not ours: dpll_pin_freq_set()=0A= reads the requested frequency as a u64 and validates it through a helper=0A= that takes a u32, so a rate of U32_MAX + 1 + N is accepted as N against=0A= the supported ranges, which are themselves u64. That affects every=0A= driver behind the interface, not just this one. It is a separate patch=0A= against the core and will be posted on its own rather than buried in a=0A= driver series; this driver range-checks its own input in the meantime.=0A= =0A= Ali Rouhi (2):=0A= dt-bindings: vendor-prefixes: add SiTime Corporation=0A= dt-bindings: dpll: add SiTime SiT95316 clock generator=0A= =0A= Oleg Zadorozhnyi (13):=0A= dpll: add basic SiTime SiT9531x support=0A= dpll: sit9531x: read DPLL types and pin properties from system=0A= firmware=0A= dpll: sit9531x: register DPLL devices and pins=0A= dpll: sit9531x: implement input pin state on a DPLL=0A= dpll: sit9531x: add support to get and set priority on input pins=0A= dpll: sit9531x: add support to get and set frequency on pins=0A= dpll: sit9531x: implement output pin state on a DPLL=0A= dpll: sit9531x: add support to adjust output phase=0A= dpll: sit9531x: add support to get and set esync on pins=0A= dpll: sit9531x: add support to get phase offset on the connected input=0A= pin=0A= dpll: sit9531x: add support to get fractional frequency offset=0A= dpll: sit9531x: model the inter-PLL sync net as a pair of pins=0A= dpll: sit9531x: allow the device tree to override two board facts=0A= =0A= .../bindings/dpll/sitime,sit95316.yaml | 181 +=0A= .../devicetree/bindings/vendor-prefixes.yaml | 2 +=0A= MAINTAINERS | 7 +=0A= drivers/dpll/Kconfig | 2 +=0A= drivers/dpll/Makefile | 1 +=0A= drivers/dpll/sit9531x/Kconfig | 17 +=0A= drivers/dpll/sit9531x/Makefile | 4 +=0A= drivers/dpll/sit9531x/core.c | 4130 +++++++++++++++++=0A= drivers/dpll/sit9531x/core.h | 407 ++=0A= drivers/dpll/sit9531x/dpll.c | 1486 ++++++=0A= drivers/dpll/sit9531x/dpll.h | 70 +=0A= drivers/dpll/sit9531x/prop.c | 437 ++=0A= drivers/dpll/sit9531x/prop.h | 39 +=0A= drivers/dpll/sit9531x/regs.h | 394 ++=0A= 14 files changed, 7177 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= create mode 100644 drivers/dpll/sit9531x/Kconfig=0A= create mode 100644 drivers/dpll/sit9531x/Makefile=0A= create mode 100644 drivers/dpll/sit9531x/core.c=0A= create mode 100644 drivers/dpll/sit9531x/core.h=0A= create mode 100644 drivers/dpll/sit9531x/dpll.c=0A= create mode 100644 drivers/dpll/sit9531x/dpll.h=0A= create mode 100644 drivers/dpll/sit9531x/prop.c=0A= create mode 100644 drivers/dpll/sit9531x/prop.h=0A= create mode 100644 drivers/dpll/sit9531x/regs.h=0A= =0A= =0A= base-commit: d0ec95a8a4e79f2fd6063fc8932415db8c227689=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=