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This series adds a DPLL subsystem driver for the SiTime SiT95316 and=0A= SiT95317 I2C clock generators. Each device integrates four PLLs with=0A= automatic reference selection and on-chip TDC phase-offset measurement,=0A= and is used for synchronization in telecom, networking, and data-center=0A= timing.=0A= =0A= The series contains the device-tree binding, the driver under=0A= drivers/dpll/sit9531x/, and the MAINTAINERS entry.=0A= =0A= v1: https://lore.kernel.org/netdev/20260511211143.19792-1-arouhi@sitime.com= /=0A= v2: https://lore.kernel.org/netdev/20260520191943.73938-1-arouhi@sitime.com= /=0A= v3: https://lore.kernel.org/netdev/20260731180951.65725-1-arouhi@sitime.com= /=0A= v4: https://lore.kernel.org/netdev/20260806232439.27551-1-arouhi@sitime.com= /=0A= v5: https://lore.kernel.org/netdev/20260810230439.22866-1-arouhi@sitime.com= /=0A= v6: https://lore.kernel.org/netdev/20260812175337.18155-1-arouhi@sitime.com= /=0A= v7: https://lore.kernel.org/netdev/20260815221919.64226-1-arouhi@sitime.com= /=0A= v8: https://lore.kernel.org/netdev/20260902214030.20955-1-arouhi@sitime.com= /=0A= v9: https://lore.kernel.org/netdev/20260915000015.80480-1-arouhi@sitime.com= /=0A= =0A= v10 follows v9 by less than a week because three things did not want to=0A= wait for a longer cycle. Carolina Jubran ran v9 on a board and found two=0A= defects in input handling. A divide-error in the frequency path turned=0A= out to be reachable from an ordinary pin get. And the embedded-sync=0A= patch is withdrawn, which takes the series from fifteen patches to=0A= fourteen.=0A= =0A= 1-2 bindings: vendor prefix, then the device schema=0A= 3 basic support: paged regmap, variant detection, probe=0A= 4 DPLL types and pin properties from system firmware=0A= 5 register the DPLL devices and pins, and keep their state=0A= 6 input pin state on a DPLL, with the pin-state contract=0A= 7 input pin priority=0A= 8 pin frequency, both directions=0A= 9 output pin state (mute)=0A= 10 output phase adjust=0A= 11 phase offset through the TDC=0A= 12 fractional frequency offset of the selected reference=0A= 13 the inter-PLL sync net as a pair of pins=0A= 14 optional device-tree overrides for two board facts=0A= =0A= The two bindings patches come first, so the driver never matches on a=0A= compatible string before the schema that describes it is in the tree.=0A= =0A= Each of the twelve driver patches builds and links on its own: no patch=0A= calls something a later patch introduces, so a bisect cannot land on a=0A= tree that fails to compile. For this posting that was re-checked patch=0A= by patch with W=3D1 and with sparse. checkpatch --strict is clean except=0A= for the "does MAINTAINERS need updating?" hint on patches 4 and 5,=0A= which add files under drivers/dpll/sit9531x/ -- patch 3 already covers=0A= that directory with an F: entry.=0A= =0A= Three things are worth reading before the changelog.=0A= =0A= The first is a divide-error, found by inspection rather than on a=0A= board. The feedback divider is a fraction, and the frequency path=0A= divided by its denominator without first establishing that the=0A= numerator was below it. The device can hold that combination from a=0A= profile the driver did not program, and the quotient then leaves what=0A= the division helper can return, which on x86 faults rather than=0A= yielding a value the caller could reject. An ordinary pin get reaches=0A= that path, so we did not want to leave it standing for a cycle. There=0A= is no trace to show; the argument is the one in the comment on=0A= sit9531x_divn_static(). The fraction is now refused instead of=0A= divided.=0A= =0A= The second is a change in behaviour that userspace can see. An output=0A= rate the divider cannot produce exactly is now refused with -EINVAL.=0A= Until v9 the driver programmed the nearest rate it could reach and=0A= reported success, so a request for a frequency this device cannot make=0A= came back as though it had been honoured. Refusing it is the smaller=0A= surprise: a caller that asked for a rate and got zero errors has no=0A= other way to learn that it is not running at that rate.=0A= =0A= The third is the withdrawal of embedded sync.=0A= =0A= Patch 11 of v9, embedded sync on pins, is dropped and not replaced.=0A= =0A= This device does not implement embedded sync. What it has in that area=0A= is SYSREF-triggered output gating with a per-output burst count, which=0A= is a different function: the byte patch 11 programmed sets how many=0A= pulses an output emits per trigger, so the 50 it wrote was a pulse=0A= count and not the 50 percent duty the getter reported. The patch had=0A= been written to the shape of the ABI rather than derived from the=0A= register, and the two quantities happen to share a literal, which is=0A= what let it look right.=0A= =0A= The automated review of v8 asked whether that write could take effect=0A= at all, given that the path never selects the SYSREF or SYNCB mode the=0A= byte belongs to. This was the right question, and the answer we gave=0A= then, and gave again for v9, was wrong. The patch is withdrawn rather=0A= than fixed, and we are not planning to resubmit it. Nothing else in the=0A= series depended on it.=0A= =0A= Changes in v10:=0A= =0A= - Arithmetic. Besides the feedback-divider fraction above, the=0A= runtime tap of that divider is now guarded the same way as the=0A= configured one, and the denominator's high bit has its own name=0A= instead of borrowing the integer field's. The device-tree override=0A= arrays are checked against the part: the VCO override needs an=0A= entry per PLL, and an output map shorter than the variant's output=0A= count is ignored rather than read as a run of unmapped outputs.=0A= =0A= - Input selection and state, from Carolina's bench report.=0A= Disconnecting the last reference now empties the priority table=0A= instead of being refused, so a DPLL can be left with no source at=0A= all. The slot encoding has codes for an input pair this part does=0A= not have, which read back as no valid reference, and every slot is=0A= given one rather than being left to read as input zero. Connected=0A= now means the device has selected the pin, not that the loop has=0A= locked to it -- those are different questions and only the first=0A= one is what the pin state answers.=0A= =0A= - Answer from the device rather than from a cache. An output's=0A= current rate comes from its divider instead of the first entry in=0A= the list of rates the board supports. The programmed phase delay is=0A= decoded from the device at probe, so a delay a profile carries can=0A= be cleared through the ABI, and it is re-read when a request could=0A= not be confirmed. The reference a phase measurement is taken=0A= against is read at the point of measurement rather than from a poll=0A= that may be a period old. The input receiver refcounts are=0A= re-derived from the priority tables the poll reads, so a request=0A= that failed part way cannot leave a receiver gated off while=0A= another PLL is still using it.=0A= =0A= - Leave the device in a state the caller can describe. A priority=0A= table that was written only in part is put back rather than=0A= latched, and the mask that is reported describes what reached the=0A= device rather than what was asked for. The forced Hi-Z pair value=0A= is written before the override, so the pad is never briefly pinned=0A= driven between the two, and the half that reached the device is=0A= released when the other did not. Ownership of the inter-PLL sync=0A= net is recorded before the read-back that can fail, and a disable=0A= that fails part way leaves the state describable so the request can=0A= be repeated. Entering the programming state closes the loops and=0A= the debug key when it fails.=0A= =0A= - Interrupt and notification. The driver gives up the interrupt line=0A= after repeated failures to clear the notification latch, rather=0A= than re-entering the handler behind a still-asserted INTRB. A=0A= change in the lock-status error is treated like a change in the=0A= status itself. Priority changes notify the sibling pins through the=0A= helper meant for a caller that already holds the device lock, leave=0A= the pin the request named to the core, and skip a pin that is being=0A= unregistered.=0A= =0A= - Output pin identity. Output pins are named and matched by the chip=0A= pin they drive rather than by the driver's index for them. The two=0A= differ on the variant whose outputs are bonded out from a subset of=0A= the slots, which is where the wrong pin would otherwise be=0A= programmed.=0A= =0A= - Binding. dpll-types is bounded to the four PLLs the part has. The=0A= example is made self-consistent with the driver: the Fvco override=0A= is on a PLL whose band the value belongs to, and is a rate the=0A= example's own output pin divides down from exactly. Patch 1 is=0A= unchanged since v8 and keeps Conor's Acked-by. Patch 2 has changed=0A= again, so Krzysztof's Reviewed-by is still not carried across it.=0A= =0A= - Housekeeping. The page selector is cached; it is the only register=0A= in the map that is not volatile, which removes a selector write per=0A= register access on a paged device. The sign handling in the output=0A= phase encoder is folded into one abs() and a remainder, and a zero=0A= offset skips the coarse and fine encoding entirely. Both of those=0A= came from Ivan Vecera. Two per-input status flags and the register=0A= read that filled them are dropped, along with a cached per-pin=0A= phase offset that was written on every path of the getter and read=0A= on none. Text that described registering DPLL devices=0A= moved to the patch that registers them. kernel-doc that had stopped=0A= listing members the structs still have is corrected.=0A= =0A= Four items from earlier rounds are unchanged and are repeated here so=0A= they are not re-raised.=0A= =0A= The phase-adjust granularity stays at 1 ps rather than the 30 ps fine=0A= step. The delays this device can reach are not a lattice of 30 ps: a=0A= request is split between a coarse delay counted in VCO cycles and a=0A= three-bit fine field of 30 ps steps, and the two are added, so the=0A= spacing depends on the VCO period in force. Advertising 30 would name=0A= a step the device does not have. A request is accepted at 1 ps and=0A= rounded to the nearest delay the registers can hold, and the getter=0A= reports what they hold rather than what was asked for, so a caller=0A= that needs the exact figure reads it back.=0A= =0A= A frequency request of 0 Hz is still refused with -EINVAL rather than=0A= treated as a request to stop the output. Nothing in the ABI says zero=0A= means off, and this device already has a mute control that says so=0A= explicitly.=0A= =0A= The use-after-free report on the pin properties remains a false=0A= positive: dpll_pin_alloc() calls dpll_pin_prop_dup(), which copies=0A= freq_supported with kmemdup() and the labels with kstrdup(), so the=0A= core owns its copies and the driver has to free its own.=0A= =0A= The u64 truncation in dpll_pin_freq_set() is still there and is still=0A= not ours to fix in this series: the requested frequency is read as a=0A= u64 and validated through a helper that takes a u32, so a rate of=0A= U32_MAX + 1 + N is accepted as N against ranges that are themselves=0A= u64. That affects every driver behind the interface. It will be posted=0A= as its own patch against the core rather than buried here; this driver=0A= range-checks its own input in the meantime.=0A= =0A= Ali Rouhi (2):=0A= dt-bindings: vendor-prefixes: add SiTime Corporation=0A= dt-bindings: dpll: add SiTime SiT95316 clock generator=0A= =0A= Oleg Zadorozhnyi (12):=0A= dpll: add basic SiTime SiT9531x support=0A= dpll: sit9531x: read DPLL types and pin properties from system=0A= firmware=0A= dpll: sit9531x: register DPLL devices and pins=0A= dpll: sit9531x: implement input pin state on a DPLL=0A= dpll: sit9531x: add support to get and set priority on input pins=0A= dpll: sit9531x: add support to get and set frequency on pins=0A= dpll: sit9531x: implement output pin state on a DPLL=0A= dpll: sit9531x: add support to adjust output phase=0A= dpll: sit9531x: add support to get phase offset on the connected input=0A= pin=0A= dpll: sit9531x: add support to get fractional frequency offset=0A= dpll: sit9531x: model the inter-PLL sync net as a pair of pins=0A= dpll: sit9531x: allow the device tree to override two board facts=0A= =0A= .../bindings/dpll/sitime,sit95316.yaml | 183 +=0A= .../devicetree/bindings/vendor-prefixes.yaml | 2 +=0A= MAINTAINERS | 7 +=0A= drivers/dpll/Kconfig | 2 +=0A= drivers/dpll/Makefile | 1 +=0A= drivers/dpll/sit9531x/Kconfig | 17 +=0A= drivers/dpll/sit9531x/Makefile | 4 +=0A= drivers/dpll/sit9531x/core.c | 4553 +++++++++++++++++=0A= drivers/dpll/sit9531x/core.h | 429 ++=0A= drivers/dpll/sit9531x/dpll.c | 1445 ++++++=0A= drivers/dpll/sit9531x/dpll.h | 66 +=0A= drivers/dpll/sit9531x/prop.c | 469 ++=0A= drivers/dpll/sit9531x/prop.h | 37 +=0A= drivers/dpll/sit9531x/regs.h | 364 ++=0A= 14 files changed, 7579 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= create mode 100644 drivers/dpll/sit9531x/Kconfig=0A= create mode 100644 drivers/dpll/sit9531x/Makefile=0A= create mode 100644 drivers/dpll/sit9531x/core.c=0A= create mode 100644 drivers/dpll/sit9531x/core.h=0A= create mode 100644 drivers/dpll/sit9531x/dpll.c=0A= create mode 100644 drivers/dpll/sit9531x/dpll.h=0A= create mode 100644 drivers/dpll/sit9531x/prop.c=0A= create mode 100644 drivers/dpll/sit9531x/prop.h=0A= create mode 100644 drivers/dpll/sit9531x/regs.h=0A= =0A= =0A= base-commit: 4bb9710c6a68d35207f123aef55dcd50e7195ec5=0A= -- =0A= 2.43.0=0A= =0A=