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Mon, 21 Sep 2026 20:11:19 +0000 From: Ali Rouhi To: "jiri@resnulli.us" CC: "vadim.fedorenko@linux.dev" , "arkadiusz.kubalewski@intel.com" , "ivecera@redhat.com" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "cjubran@nvidia.com" , "pabeni@redhat.com" , "Oleg.Zadorozhnyi@devoxsoftware.com" , "prabhakar.mahadev-lad.rj@bp.renesas.com" , "dev@kael-k.io" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Ali Rouhi Subject: [PATCH v10 13/14] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Thread-Topic: [PATCH v10 13/14] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Thread-Index: AQHdSgVc40qUlDeCzkytlQ8xnxUSgQ== Date: Mon, 21 Sep 2026 20:11:18 +0000 Message-ID: <20260921201108.42676-14-arouhi@sitime.com> References: <20260921201108.42676-1-arouhi@sitime.com> In-Reply-To: <20260921201108.42676-1-arouhi@sitime.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=sitime.com; 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From: Oleg Zadorozhnyi =0A= =0A= The device has an internal net by which one PLL can drive the others: the= =0A= source PLL puts its output on it, and any other PLL can select it as a=0A= reference instead of an external input. The two ends are nothing alike --= =0A= one is driven, the other is selected -- so they are two pins rather than=0A= one: an output pin on the source and an input pin on each destination.=0A= =0A= That keeps each pin honest about what its state means. The source pin=0A= reports whether this PLL is the one driving the net, and setting it takes= =0A= the net over or gives it up; a destination pin reports whether its PLL has= =0A= selected the net, and behaves like any other selectable input. A single=0A= pin would have had to answer both questions at once and could only have=0A= been right about one of them.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Assisted-by: Claude:claude-4-opus [chat]=0A= Signed-off-by: Ali Rouhi =0A= ---=0A= =0A= Notes:=0A= Changes in v10:=0A= INTSYNC ownership: recorded before the read-back that can fail, and a= =0A= disable that fails part way leaves the state describable so the request= =0A= can be repeated.=0A= =0A= Error reporting: a full priority table says so instead of reading like = a=0A= bus failure.=0A= =0A= drivers/dpll/sit9531x/core.c | 291 ++++++++++++++++++++++++++++++++++-=0A= drivers/dpll/sit9531x/core.h | 3 +=0A= drivers/dpll/sit9531x/dpll.c | 247 ++++++++++++++++++++++++++++-=0A= drivers/dpll/sit9531x/regs.h | 3 +=0A= 4 files changed, 538 insertions(+), 6 deletions(-)=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c=0A= index 1cb691f04019..e8d47999f1a9 100644=0A= --- a/drivers/dpll/sit9531x/core.c=0A= +++ b/drivers/dpll/sit9531x/core.c=0A= @@ -2264,9 +2264,9 @@ int sit9531x_output_freq_get(struct sit9531x_dev *sit= dev, u8 out_idx,=0A= * block at base =3D 0x15 + 16 * (slot % 6); the slot is the physical=0A= * output position from clkout_map[], not the logical output index.=0A= *=0A= - * The chip only supports unsigned positive delay. A negative phase=0A= - * adjustment (advance) is wrapped to (T_out - |phase|) modulo one=0A= - * output period, which is identical for a periodic signal.=0A= + * The chip only supports unsigned positive delay. Requests are folded=0A= + * modulo one output period: positive delays wrap naturally and a negative= =0A= + * phase adjustment (advance) is rendered as (T_out - |phase|).=0A= */=0A= =0A= int sit9531x_output_phase_adjust_set(struct sit9531x_dev *sitdev,=0A= @@ -2531,6 +2531,278 @@ int sit9531x_clear_notifications(struct sit9531x_de= v *sitdev)=0A= return 0;=0A= }=0A= =0A= +/*=0A= + * INTSYNC configuration register values.=0A= + * These are written to the source PLL's EXT page to enable/disable=0A= + * inter-PLL synchronization (lock frequency PLL to phase PLL).=0A= + */=0A= +struct sit9531x_intsync_reg {=0A= + u8 offset;=0A= + u8 en_val;=0A= + u8 dis_val;=0A= +};=0A= +=0A= +static const struct sit9531x_intsync_reg intsync_config[] =3D {=0A= + { 0x2D, 0x02, 0x00 },=0A= + { 0x50, 0x08, 0x00 },=0A= + { 0x51, 0x04, 0x00 },=0A= + { 0x54, 0x02, 0x00 },=0A= + { 0x55, 0x28, 0x20 },=0A= + { 0x5C, 0x0F, 0x00 },=0A= + { 0x5D, 0xFF, 0x00 },=0A= + { 0x6C, 0xDD, 0x00 },=0A= +};=0A= +=0A= +int sit9531x_intsync_src_detect(struct sit9531x_dev *sitdev)=0A= +{=0A= + s8 src =3D -1;=0A= + u8 global;=0A= + u8 pll, ext_page;=0A= + int rc, i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &global);=0A= + if (rc)=0A= + return rc;=0A= +=0A= + if (!(global & BIT(SIT9531X_INTSYNC_EN_BIT))) {=0A= + sitdev->intsync_src =3D -1;=0A= + return 0;=0A= + }=0A= +=0A= + for (pll =3D 0; pll < SIT9531X_NUM_PLLS; pll++) {=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(pll);=0A= +=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + u16 reg;=0A= + u8 val;=0A= +=0A= + reg =3D SIT9531X_REG(ext_page, intsync_config[i].offset);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, reg, &val);=0A= + if (rc)=0A= + return rc;=0A= + if (val !=3D intsync_config[i].en_val)=0A= + break;=0A= + }=0A= +=0A= + if (i =3D=3D ARRAY_SIZE(intsync_config)) {=0A= + /*=0A= + * Only one PLL can drive the net. If a second=0A= + * one matches, the registers are not describing=0A= + * a state this driver put the device in, so say=0A= + * so rather than pick silently.=0A= + */=0A= + if (src < 0)=0A= + src =3D pll;=0A= + else=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c also matches the INTSYNC source pattern; keeping PLL%c\n",=0A= + 'A' + pll, 'A' + src);=0A= + }=0A= + }=0A= +=0A= + sitdev->intsync_src =3D src;=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * Close the debug window on a PLL's EXT page. The key register opens=0A= + * every debug register on that page while it holds the unlock value.=0A= + */=0A= +static int sit9531x_intsync_debug_lock(struct sit9531x_dev *sitdev, u8 ext= _page)=0A= +{=0A= + return sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page, SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_LOCK);=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_intsync_enable - enable inter-PLL synchronization=0A= + * @src_pll_idx: source (frequency) PLL index (0-3)=0A= + *=0A= + * Enables INTSYNC global bit, unlocks the source PLL's EXT page=0A= + * debug registers, writes configuration, and triggers a small=0A= + * update on the source PLL.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_intsync_enable(struct sit9531x_dev *sitdev, u8 src_pll_idx)= =0A= +{=0A= + u8 ext_page, val;=0A= + int rc, lock_rc, i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (src_pll_idx >=3D SIT9531X_NUM_PLLS)=0A= + return -EINVAL;=0A= +=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(src_pll_idx);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val);=0A= + if (rc)=0A= + return rc;=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val | BIT(SIT9531X_INTSYNC_EN_BIT));=0A= + if (rc)=0A= + return rc;=0A= +=0A= + /* Small update on Page 0 */=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_GLOBAL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + usleep_range(1000, 2000);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + /* Unlock debug on EXT page */=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + intsync_config[i].offset),=0A= + intsync_config[i].en_val);=0A= + if (rc)=0A= + goto relock_err;=0A= + }=0A= +=0A= + /* Small update on source PLL */=0A= + rc =3D sit9531x_write_pll_u8(sitdev, src_pll_idx,=0A= + SIT9531X_PLL_REG_SMALL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + rc =3D 0;=0A= + goto relock;=0A= +=0A= +relock_err:=0A= + sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + goto err_disable;=0A= +=0A= +relock:=0A= + /*=0A= + * Close the EXT page debug window the sequence opened. Nothing=0A= + * else writes the key back, so leaving it open would keep the block=0A= + * unlocked for as long as the device runs.=0A= + */=0A= + lock_rc =3D sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + if (lock_rc && !rc)=0A= + rc =3D lock_rc;=0A= +=0A= + return rc;=0A= +=0A= +err_disable:=0A= + /*=0A= + * The global enable is already set at this point. The caller only=0A= + * records the source PLL when this function succeeds, so nothing=0A= + * else will ever clear the bit: undo it here rather than leave the=0A= + * net asserted with a half-written EXT page.=0A= + */=0A= + {=0A= + int rollback_rc;=0A= +=0A= + rollback_rc =3D sit9531x_intsync_disable(sitdev, src_pll_idx);=0A= + if (rollback_rc)=0A= + dev_warn(sitdev->dev,=0A= + "INTSYNC rollback failed after enable error: %d (original %d)\n",=0A= + rollback_rc, rc);=0A= + }=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_intsync_disable - disable inter-PLL synchronization=0A= + * @src_pll_idx: source (frequency) PLL index (0-3)=0A= + *=0A= + * Clears INTSYNC global bit, writes disable values to the source=0A= + * PLL's EXT page, and triggers a small update.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_intsync_disable(struct sit9531x_dev *sitdev, u8 src_pll_idx)= =0A= +{=0A= + u8 ext_page, val;=0A= + int rc, lock_rc, i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (src_pll_idx >=3D SIT9531X_NUM_PLLS)=0A= + return -EINVAL;=0A= +=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(src_pll_idx);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val);=0A= + if (rc)=0A= + return rc;=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val & ~BIT(SIT9531X_INTSYNC_EN_BIT));=0A= + if (rc)=0A= + return rc;=0A= +=0A= + /* Small update on Page 0 */=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_GLOBAL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + usleep_range(1000, 2000);=0A= + if (rc)=0A= + return rc;=0A= +=0A= + /* Unlock debug on EXT page */=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + goto relock;=0A= +=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + intsync_config[i].offset),=0A= + intsync_config[i].dis_val);=0A= + if (rc)=0A= + goto restore_global;=0A= + }=0A= +=0A= + /* Small update on source PLL */=0A= + rc =3D sit9531x_write_pll_u8(sitdev, src_pll_idx,=0A= + SIT9531X_PLL_REG_SMALL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + if (rc)=0A= + goto relock;=0A= +=0A= + rc =3D 0;=0A= +=0A= +restore_global:=0A= + /*=0A= + * The global enable was cleared first, so a failure here leaves the=0A= + * EXT page still holding the enable pattern with nothing pointing=0A= + * at it: the source detector keys on the global bit, would report=0A= + * the net as unowned, and a retry of the disable would then=0A= + * short-circuit. Put the bit back so the state stays one the=0A= + * driver can describe and the request can be repeated.=0A= + */=0A= + if (!sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val))=0A= + sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val | BIT(SIT9531X_INTSYNC_EN_BIT));=0A= +=0A= +relock:=0A= + /* Close the EXT page debug window the sequence opened. */=0A= + lock_rc =3D sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + if (lock_rc && !rc)=0A= + rc =3D lock_rc;=0A= +=0A= + return rc;=0A= +}=0A= +=0A= /**=0A= * sit9531x_chan_selected_ref_read - read a PLL's active reference now=0A= * @sitdev: device pointer=0A= @@ -3109,6 +3381,15 @@ static int sit9531x_dev_state_fetch(struct sit9531x_= dev *sitdev)=0A= return rc;=0A= }=0A= =0A= + mutex_lock(&sitdev->multiop_lock);=0A= + rc =3D sit9531x_intsync_src_detect(sitdev);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= + if (rc) {=0A= + dev_err(sitdev->dev,=0A= + "Failed to detect INTSYNC source: %d\n", rc);=0A= + return rc;=0A= + }=0A= +=0A= for (i =3D 0; i < sitdev->info->num_outputs; i++) {=0A= s32 phase_ps;=0A= =0A= @@ -3664,13 +3945,13 @@ static bool sit9531x_dpll_pin_is_registrable(struct= sit9531x_dpll *sitdpll,=0A= if (index =3D=3D SIT9531X_MAX_INPUTS)=0A= return true;=0A= if (index =3D=3D SIT9531X_INTSYNC_PIN_ID)=0A= - return false;=0A= + return true;=0A= =0A= return sit9531x_input_pin_is_registrable(sitdev, index);=0A= }=0A= =0A= if (index =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID)=0A= - return false;=0A= + return true;=0A= =0A= if (index >=3D sitdev->info->num_outputs)=0A= return false;=0A= diff --git a/drivers/dpll/sit9531x/core.h b/drivers/dpll/sit9531x/core.h=0A= index 1d77b89e83ec..1fc14eabb621 100644=0A= --- a/drivers/dpll/sit9531x/core.h=0A= +++ b/drivers/dpll/sit9531x/core.h=0A= @@ -287,6 +287,9 @@ int sit9531x_output_phase_adjust_set(struct sit9531x_de= v *sitdev,=0A= int sit9531x_clear_notifications(struct sit9531x_dev *sitdev);=0A= =0A= /* ---- INTSYNC (inter-PLL synchronization) ---- */=0A= +int sit9531x_intsync_enable(struct sit9531x_dev *sitdev, u8 src_pll_idx);= =0A= +int sit9531x_intsync_disable(struct sit9531x_dev *sitdev, u8 src_pll_idx);= =0A= +int sit9531x_intsync_src_detect(struct sit9531x_dev *sitdev);=0A= =0A= /* ---- Phase offset (TDC readback) ---- */=0A= int sit9531x_pll_ffo_ppt(struct sit9531x_dev *sitdev, u8 pll_idx, s64 *ffo= );=0A= diff --git a/drivers/dpll/sit9531x/dpll.c b/drivers/dpll/sit9531x/dpll.c=0A= index fcdd19e0bd3b..856c9bdf33d4 100644=0A= --- a/drivers/dpll/sit9531x/dpll.c=0A= +++ b/drivers/dpll/sit9531x/dpll.c=0A= @@ -27,6 +27,20 @@ static bool sit9531x_dpll_is_input_pin(const struct sit9= 531x_dpll_pin *pin)=0A= return pin->dir =3D=3D DPLL_PIN_DIRECTION_INPUT;=0A= }=0A= =0A= +static bool=0A= +sit9531x_dpll_is_intsync_pin(const struct sit9531x_dpll_pin *pin)=0A= +{=0A= + return sit9531x_dpll_is_input_pin(pin) &&=0A= + pin->id =3D=3D SIT9531X_INTSYNC_PIN_ID;=0A= +}=0A= +=0A= +static bool=0A= +sit9531x_dpll_is_intsync_src_pin(const struct sit9531x_dpll_pin *pin)=0A= +{=0A= + return !sit9531x_dpll_is_input_pin(pin) &&=0A= + pin->id =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID;=0A= +}=0A= +=0A= static bool=0A= sit9531x_dpll_is_xo_pin(const struct sit9531x_dpll_pin *pin)=0A= {=0A= @@ -843,8 +857,234 @@ sit9531x_dpll_output_pin_direction_get(const struct d= pll_pin *pin,=0A= enum dpll_pin_direction *direction,=0A= struct netlink_ext_ack *extack);=0A= =0A= +static int=0A= +sit9531x_dpll_intsync_src_state_on_dpll_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state *state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id)=0A= + *state =3D DPLL_PIN_STATE_CONNECTED;=0A= + else=0A= + *state =3D DPLL_PIN_STATE_DISCONNECTED;=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_dpll_intsync_src_state_on_dpll_set - drive INTSYNC from a PLL= =0A= + *=0A= + * CONNECTED -> this PLL drives the INTSYNC net=0A= + * DISCONNECTED -> stop driving INTSYNC if this PLL drives it=0A= + *=0A= + * SELECTABLE is rejected: driving the net is an explicit output routing,= =0A= + * not an automatic-selection candidate, matching the regular output pin.= =0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_src_state_on_dpll_set(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + int rc =3D 0, detect_rc =3D 0;=0A= + u8 hw_src;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + switch (state) {=0A= + case DPLL_PIN_STATE_CONNECTED:=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id)=0A= + break;=0A= + if (sitdev->intsync_src >=3D 0) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "INTSYNC is already sourced by another PLL");=0A= + rc =3D -EBUSY;=0A= + break;=0A= + }=0A= + /*=0A= + * A PLL that already lists INTSYNC among its references must=0A= + * not also drive it: the destination side refuses the mirror=0A= + * of this, and without the check here the net could be routed=0A= + * back into the PLL feeding it.=0A= + */=0A= + hw_src =3D sit9531x_input_hw_src(SIT9531X_INTSYNC_PIN_ID);=0A= + if (sit9531x_input_prio_present(sitdev, sitdpll->id, hw_src)) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "PLL selects INTSYNC as a reference; it cannot drive it");=0A= + rc =3D -EBUSY;=0A= + break;=0A= + }=0A= + rc =3D sit9531x_intsync_enable(sitdev, sitdpll->id);=0A= + break;=0A= + case DPLL_PIN_STATE_DISCONNECTED:=0A= + if (sitdev->intsync_src !=3D sitdpll->id)=0A= + break;=0A= + rc =3D sit9531x_intsync_disable(sitdev, sitdpll->id);=0A= + break;=0A= + default:=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= +=0A= + /*=0A= + * Re-scan hardware after source state transitions so cache follows=0A= + * partially failed enable/disable paths as closely as possible.=0A= + */=0A= + /*=0A= + * Record what was asked for before confirming it. The refresh below=0A= + * leaves the cache untouched when a read fails, and a cache that=0A= + * still says nobody drives the net would let a second PLL be=0A= + * configured to drive it as well.=0A= + */=0A= + if (!rc && state =3D=3D DPLL_PIN_STATE_CONNECTED)=0A= + sitdev->intsync_src =3D sitdpll->id;=0A= + else if (!rc && state =3D=3D DPLL_PIN_STATE_DISCONNECTED)=0A= + sitdev->intsync_src =3D -1;=0A= +=0A= + if (state =3D=3D DPLL_PIN_STATE_CONNECTED ||=0A= + state =3D=3D DPLL_PIN_STATE_DISCONNECTED)=0A= + detect_rc =3D sit9531x_intsync_src_detect(sitdev);=0A= + /*=0A= + * The refresh only re-reads what the device now shows. Failing=0A= + * the request because that read hit a bus error would tell=0A= + * userspace the enable did not happen when it did.=0A= + */=0A= + if (detect_rc)=0A= + dev_warn(sitdev->dev,=0A= + "INTSYNC source cache not refreshed: %d\n",=0A= + detect_rc);=0A= +=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + if (rc && rc !=3D -EBUSY && rc !=3D -EINVAL && rc !=3D -EOPNOTSUPP)=0A= + NL_SET_ERR_MSG(extack, "Failed to set INTSYNC source state");=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +static const struct dpll_pin_ops sit9531x_dpll_intsync_src_pin_ops =3D {= =0A= + .direction_get =3D sit9531x_dpll_output_pin_direction_get,=0A= + .state_on_dpll_get =3D sit9531x_dpll_intsync_src_state_on_dpll_get,=0A= + .state_on_dpll_set =3D sit9531x_dpll_intsync_src_state_on_dpll_set,=0A= +};=0A= +=0A= /* ---- INTSYNC destination (input) pin ---- */=0A= =0A= +/*=0A= + * sit9531x_dpll_intsync_dst_state_on_dpll_get - INTSYNC reference state= =0A= + *=0A= + * Selection role, so the contract above decides this exactly as it does= =0A= + * for a physical input: the priority table is the eligibility record, and= =0A= + * whether a source PLL happens to be driving the net right now is no more= =0A= + * a state than a momentary LOS is on an external reference. The one=0A= + * addition is that the PLL driving INTSYNC is never its own destination.= =0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_dst_state_on_dpll_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state *state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id)=0A= + *state =3D DPLL_PIN_STATE_DISCONNECTED;=0A= + else=0A= + sit9531x_dpll_selection_state_get(sitdev, sitdpll,=0A= + SIT9531X_INTSYNC_PIN_ID,=0A= + state);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_dpll_intsync_dst_state_on_dpll_set - lock a PLL to INTSYNC=0A= + *=0A= + * Selection role, so this accepts and refuses what a physical input does,= =0A= + * CONNECTED included: the device pins no reference on request whichever= =0A= + * source is asked for. INTSYNC is an internal net with no physical=0A= + * receiver, so only the per-PLL priority table is touched; the source pin= =0A= + * controls generation.=0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_dst_state_on_dpll_set(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + u8 hw_src =3D sit9531x_input_hw_src(SIT9531X_INTSYNC_PIN_ID);=0A= + int rc;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + switch (state) {=0A= + case DPLL_PIN_STATE_DISCONNECTED:=0A= + rc =3D sit9531x_input_prio_remove(sitdev, sitdpll->id, hw_src);=0A= + break;=0A= + case DPLL_PIN_STATE_CONNECTED:=0A= + NL_SET_ERR_MSG(extack,=0A= + "Device selects its reference by priority; use selectable");=0A= + rc =3D -EOPNOTSUPP;=0A= + break;=0A= + case DPLL_PIN_STATE_SELECTABLE:=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "PLL cannot lock to the INTSYNC it drives");=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= + rc =3D sit9531x_input_prio_add(sitdev, sitdpll->id, hw_src);=0A= + break;=0A= + default:=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= +=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + if (rc =3D=3D -ENOSPC)=0A= + NL_SET_ERR_MSG(extack,=0A= + "Priority table is full of unique sources on this PLL");=0A= + else if (rc && rc !=3D -EINVAL && rc !=3D -EOPNOTSUPP)=0A= + NL_SET_ERR_MSG(extack, "Failed to set INTSYNC input state");=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +/*=0A= + * Do not add .frequency_get / the generic input state getter here: the=0A= + * destination pin id is SIT9531X_INTSYNC_PIN_ID, one past the end of the= =0A= + * ref[] array (INTSYNC is an internal net with no ref[] entry). The ops= =0A= + * below only ever key on chan[] and the priority table, never ref[id].=0A= + */=0A= +static const struct dpll_pin_ops sit9531x_dpll_intsync_dst_pin_ops =3D {= =0A= + .direction_get =3D sit9531x_dpll_input_pin_direction_get,=0A= + .state_on_dpll_get =3D sit9531x_dpll_intsync_dst_state_on_dpll_get,=0A= + .state_on_dpll_set =3D sit9531x_dpll_intsync_dst_state_on_dpll_set,=0A= + .prio_get =3D sit9531x_dpll_input_pin_prio_get,=0A= + .prio_set =3D sit9531x_dpll_input_pin_prio_set,=0A= +};=0A= +=0A= /*=0A= * XO (crystal oscillator) pin ops=0A= *=0A= @@ -1126,8 +1366,13 @@ static const struct dpll_pin_ops sit9531x_dpll_outpu= t_pin_ops =3D {=0A= const struct dpll_pin_ops *=0A= sit9531x_dpll_pin_ops_get(const struct sit9531x_dpll_pin *pin)=0A= {=0A= - if (!sit9531x_dpll_is_input_pin(pin))=0A= + if (!sit9531x_dpll_is_input_pin(pin)) {=0A= + if (sit9531x_dpll_is_intsync_src_pin(pin))=0A= + return &sit9531x_dpll_intsync_src_pin_ops;=0A= return &sit9531x_dpll_output_pin_ops;=0A= + }=0A= + if (sit9531x_dpll_is_intsync_pin(pin))=0A= + return &sit9531x_dpll_intsync_dst_pin_ops;=0A= if (sit9531x_dpll_is_xo_pin(pin))=0A= return &sit9531x_dpll_xo_pin_ops;=0A= return &sit9531x_dpll_input_pin_ops;=0A= diff --git a/drivers/dpll/sit9531x/regs.h b/drivers/dpll/sit9531x/regs.h=0A= index 4a928126473d..09a2032f7bf0 100644=0A= --- a/drivers/dpll/sit9531x/regs.h=0A= +++ b/drivers/dpll/sit9531x/regs.h=0A= @@ -315,6 +315,9 @@=0A= #define SIT9531X_PLL_REG_ACTIVE 0x02=0A= #define SIT9531X_PLL_ACTIVE_BIT BIT(0) /* PLL reached active state */=0A= =0A= +/* PLL EXT page INTSYNC configuration registers */=0A= +#define SIT9531X_PLL_EXT_PAGE(_idx) (SIT9531X_PAGE_PLLA_EXT + (_idx))=0A= +=0A= #define SIT9531X_PLL_STATUS_OUTER_DIS BIT(5)=0A= =0A= /*=0A= -- =0A= 2.43.0=0A= =0A=