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From: Oleg Zadorozhnyi =0A= =0A= Two things the driver reads from the chip can be wrong on a board, and=0A= neither has anywhere else to come from.=0A= =0A= The VCO frequency is derived from the feedback divider, which is exact=0A= while the loop runs but not while a PLL sits in free-run with a divider=0A= the configuration never programmed; a board that knows its own VCO can=0A= state it. The output-to-PLL routing is read from the output map=0A= registers, which describe what the loaded configuration did -- and a board= =0A= whose outputs are fanned out differently from what those registers imply=0A= can state that too.=0A= =0A= Both are optional. Absent the properties the driver behaves exactly as=0A= before, deriving one and reading the other.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Assisted-by: Claude:claude-4-opus [chat]=0A= Signed-off-by: Ali Rouhi =0A= ---=0A= =0A= Notes:=0A= Changes in v10:=0A= Checked the device-tree array lengths against the part: the VCO=0A= override needs an entry per PLL, and an output map shorter than the=0A= variant's output count is ignored rather than read as unmapped=0A= outputs.=0A= =0A= Updated the accessor's kernel-doc, which no longer described the=0A= override path.=0A= =0A= drivers/dpll/sit9531x/core.c | 171 ++++++++++++++++++++++++++++++++++-=0A= drivers/dpll/sit9531x/core.h | 1 +=0A= 2 files changed, 167 insertions(+), 5 deletions(-)=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c=0A= index e8d47999f1a9..5316e6bcb338 100644=0A= --- a/drivers/dpll/sit9531x/core.c=0A= +++ b/drivers/dpll/sit9531x/core.c=0A= @@ -1695,12 +1695,15 @@ int sit9531x_pll_ffo_ppt(struct sit9531x_dev *sitde= v, u8 pll_idx, s64 *ffo)=0A= }=0A= =0A= /*=0A= - * sit9531x_get_fvco - read VCO frequency from chip's DIVN registers=0A= + * sit9531x_get_fvco - the VCO frequency the driver works from=0A= *=0A= - * Fvco =3D Fref * DIVN, where DIVN comes from sit9531x_divn_static() and= =0A= - * Fref =3D xtal_freq << doubler. DIVN is the steady-state Fvco/Fref=0A= - * target programmed by the NVM blob and is authoritative in both=0A= - * free-run and sync modes.=0A= + * A board that describes the VCO through "sitime,pll-fvco" is taken at=0A= + * its word and nothing is read. Otherwise Fvco =3D Fref * DIVN, where=0A= + * DIVN comes from sit9531x_divn_static() and Fref =3D xtal_freq <<=0A= + * doubler. DIVN is the steady-state Fvco/Fref target programmed by the= =0A= + * NVM blob and is authoritative in both free-run and sync modes; the=0A= + * result is clamped to the band the PLL runs in, so every caller divides= =0A= + * the same number.=0A= *=0A= * Return: 0 with *fvco set on success, -ENODATA when DIVN is not=0A= * programmed (dormant PLL), or the register access error. A bus=0A= @@ -3238,6 +3241,27 @@ static int sit9531x_out_state_fetch(struct sit9531x_= dev *sitdev, u8 index)=0A= =0A= sitdev->out[index].state_stale =3D false;=0A= =0A= + /*=0A= + * DT board-config override: the per-PLL OUTPUT_ENABLE bitmaps=0A= + * (0x27/0x28) do not unambiguously express output->PLL routing on=0A= + * every config (overlaps, and some outputs routed outside that=0A= + * path). When the board supplies an explicit map, trust it.=0A= + */=0A= + if (sitdev->out_pll_map_valid) {=0A= + u8 m =3D sitdev->out_pll_map[index];=0A= +=0A= + if (m < SIT9531X_NUM_PLLS) {=0A= + out->pll_idx =3D m;=0A= + out->routed =3D true;=0A= + out->enabled =3D !muted;=0A= + } else {=0A= + out->pll_idx =3D 0;=0A= + out->routed =3D false;=0A= + out->enabled =3D false;=0A= + }=0A= + return 0;=0A= + }=0A= +=0A= /*=0A= * The OUT_MAP_LO/HI bitmaps are indexed by the physical slot the=0A= * output occupies on the chip, not by the driver's logical output=0A= @@ -4223,6 +4247,126 @@ static u64 sit9531x_derive_clock_id(struct sit9531x= _dev *sitdev)=0A= return clkid;=0A= }=0A= =0A= +/*=0A= + * Does an Fvco fall in the band the given PLL runs in?=0A= + *=0A= + * The two bands are disjoint, and which one applies is fixed per PLL, so = a=0A= + * single envelope from the bottom of the low band to the top of the high= =0A= + * one would accept both the ~1 GHz gap between them and a rate belonging = to=0A= + * the other PLL's band.=0A= + */=0A= +static bool sit9531x_fvco_in_band(u8 pll_idx, u64 fvco)=0A= +{=0A= + if (pll_idx =3D=3D 1 || pll_idx =3D=3D 3)=0A= + return fvco >=3D SIT9531X_FVCO_HIGHBAND_MIN &&=0A= + fvco <=3D SIT9531X_FVCO_HIGHBAND_MAX;=0A= +=0A= + return fvco >=3D SIT9531X_FVCO_LOWBAND_MIN &&=0A= + fvco <=3D SIT9531X_FVCO_LOWBAND_MAX;=0A= +}=0A= +=0A= +/*=0A= + * Board-config overrides for fixed efuse/blob routing the chip registers = do=0A= + * not describe unambiguously. Absent properties leave pll_fvco[] zeroed= =0A= + * (derive from DIVN) and out_pll_map_valid false (use the OUT_MAP registe= rs).=0A= + */=0A= +static void sit9531x_parse_board_config(struct sit9531x_dev *sitdev)=0A= +{=0A= + u32 map[SIT9531X_MAX_OUTPUTS];=0A= + int n, i, rc;=0A= +=0A= + if (device_property_present(sitdev->dev, "sitime,pll-fvco")) {=0A= + /*=0A= + * A fixed-count read rejects a short array but accepts a=0A= + * long one and drops the surplus, so the count is checked=0A= + * here: the property describes four PLLs and an array of=0A= + * any other length describes something else.=0A= + */=0A= + rc =3D device_property_count_u64(sitdev->dev,=0A= + "sitime,pll-fvco");=0A= + if (rc !=3D SIT9531X_NUM_PLLS) {=0A= + dev_warn(sitdev->dev,=0A= + "sitime,pll-fvco needs %d entries, ignoring\n",=0A= + SIT9531X_NUM_PLLS);=0A= + memset(sitdev->pll_fvco, 0, sizeof(sitdev->pll_fvco));=0A= + goto out_map;=0A= + }=0A= +=0A= + rc =3D device_property_read_u64_array(sitdev->dev,=0A= + "sitime,pll-fvco",=0A= + sitdev->pll_fvco,=0A= + SIT9531X_NUM_PLLS);=0A= + if (rc) {=0A= + dev_warn(sitdev->dev,=0A= + "invalid sitime,pll-fvco (%d), ignoring\n",=0A= + rc);=0A= + memset(sitdev->pll_fvco, 0, sizeof(sitdev->pll_fvco));=0A= + }=0A= +=0A= + /*=0A= + * The override is used verbatim by the divider math, so an=0A= + * implausible value (units typo, wrong cell count worked=0A= + * around with zeros) must not silently misprogram DIVO.=0A= + * Anything outside both VCO bands is dropped with a warning=0A= + * rather than trusted.=0A= + */=0A= + for (i =3D 0; i < SIT9531X_NUM_PLLS; i++) {=0A= + u64 f =3D sitdev->pll_fvco[i];=0A= +=0A= + if (f && !sit9531x_fvco_in_band(i, f)) {=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c Fvco override %llu Hz is outside the band that PLL runs in, i= gnoring\n",=0A= + 'A' + i, f);=0A= + sitdev->pll_fvco[i] =3D 0;=0A= + }=0A= + }=0A= + }=0A= +=0A= +out_map:=0A= + if (!device_property_present(sitdev->dev, "sitime,output-pll-map"))=0A= + return;=0A= +=0A= + /*=0A= + * Any 1..MAX_OUTPUTS length is accepted so the 8-output SiT95317 need=0A= + * not pad to 12; variant detection has not run yet and entries past=0A= + * the detected num_outputs are never indexed. Trailing entries of a=0A= + * short map must read as unmapped rather than 0 (=3D=3D PLLA), which=0A= + * would mark unrouted outputs active in sit9531x_out_state_fetch().=0A= + */=0A= + memset(sitdev->out_pll_map, SIT9531X_OUT_PLL_UNMAPPED,=0A= + sizeof(sitdev->out_pll_map));=0A= +=0A= + n =3D device_property_count_u32(sitdev->dev, "sitime,output-pll-map");=0A= + sitdev->out_pll_map_count =3D (n > 0) ? n : 0;=0A= + if (n <=3D 0 || n > SIT9531X_MAX_OUTPUTS ||=0A= + device_property_read_u32_array(sitdev->dev, "sitime,output-pll-map",= =0A= + map, n)) {=0A= + dev_warn(sitdev->dev,=0A= + "invalid sitime,output-pll-map, ignoring\n");=0A= + return;=0A= + }=0A= +=0A= + /*=0A= + * The binding allows only 0-3 and 255 per entry. A stray value=0A= + * would silently unroute an output (m >=3D SIT9531X_NUM_PLLS reads=0A= + * as unmapped in sit9531x_out_state_fetch()), so reject the whole=0A= + * property loudly instead.=0A= + */=0A= + for (i =3D 0; i < n; i++) {=0A= + if (map[i] >=3D SIT9531X_NUM_PLLS &&=0A= + map[i] !=3D SIT9531X_OUT_PLL_UNMAPPED) {=0A= + dev_warn(sitdev->dev,=0A= + "sitime,output-pll-map entry %d is %u (must be 0-3 or 255), ignoring = map\n",=0A= + i, map[i]);=0A= + return;=0A= + }=0A= + }=0A= +=0A= + for (i =3D 0; i < n; i++)=0A= + sitdev->out_pll_map[i] =3D map[i];=0A= + sitdev->out_pll_map_valid =3D true;=0A= +}=0A= +=0A= int sit9531x_dev_probe(struct sit9531x_dev *sitdev)=0A= {=0A= struct clk *xtal_clk;=0A= @@ -4267,6 +4411,8 @@ int sit9531x_dev_probe(struct sit9531x_dev *sitdev)= =0A= if (sitdev->reset_gpio)=0A= fsleep(10000); /* internal boot after release */=0A= =0A= + sit9531x_parse_board_config(sitdev);=0A= +=0A= rc =3D sit9531x_read_variant_id(sitdev, &variant_id);=0A= if (rc)=0A= return rc;=0A= @@ -4277,6 +4423,21 @@ int sit9531x_dev_probe(struct sit9531x_dev *sitdev)= =0A= "Unknown variant ID: 0x%02x\n",=0A= variant_id);=0A= =0A= + /*=0A= + * The map is parsed before the variant is known, so its length can=0A= + * only be checked against the part here. A map that stops short of=0A= + * the outputs this variant has leaves the rest reading as unmapped,=0A= + * which would drop real output pins; fall back to the routing the=0A= + * registers describe instead.=0A= + */=0A= + if (sitdev->out_pll_map_valid &&=0A= + sitdev->out_pll_map_count < sitdev->info->num_outputs) {=0A= + dev_warn(sitdev->dev,=0A= + "sitime,output-pll-map has %u of %u outputs, ignoring map\n",=0A= + sitdev->out_pll_map_count, sitdev->info->num_outputs);=0A= + sitdev->out_pll_map_valid =3D false;=0A= + }=0A= +=0A= sitdev->clock_id =3D sit9531x_derive_clock_id(sitdev);=0A= sitdev->intsync_src =3D -1;=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.h b/drivers/dpll/sit9531x/core.h=0A= index 1fc14eabb621..31a5f49c0253 100644=0A= --- a/drivers/dpll/sit9531x/core.h=0A= +++ b/drivers/dpll/sit9531x/core.h=0A= @@ -224,6 +224,7 @@ struct sit9531x_dev {=0A= u64 pll_fvco[SIT9531X_NUM_PLLS];=0A= u8 out_pll_map[SIT9531X_MAX_OUTPUTS];=0A= bool out_pll_map_valid;=0A= + u8 out_pll_map_count;=0A= =0A= /* Inter-PLL synchronization state */=0A= s8 intsync_src;=0A= -- =0A= 2.43.0=0A= =0A=