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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c6f5asm11080466b.15.2026.09.22.13.27.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 13:27:05 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, ansuelsmth@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, florian.fainelli@broadcom.com, jonas.gorski@gmail.com, woojung.huh@microchip.com, UNGLinuxDriver@microchip.com, hzyitc@outlook.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, Yongzhao Chen Subject: [RFC PATCH net-next v2 0/5] net: dsa: qca8k: add a QCA8337 CPU PHY consumer Date: Tue, 22 Sep 2026 22:26:48 +0200 Message-ID: <20260922202653.1153-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Following Andrew's feedback on the v1 RFC, shared-port PHY flag plumbing now includes its consumer within the same series. To clarify a prior misunderstanding, the qca83xx PHY driver already exists upstream; patch 5 supplies the new flag consumer alongside internal CPU-PHY selection in qca8k. The minimal topology has one CPU link: a conduit PHY connects through MDI to QCA8337 PHY4, belonging to switch port 5. The two sides have distinct phy-handles. A user port provides the data path; ports 0 and 6 are unused. The existing binding accepts an ethernet phandle, phy-mode and phy-handle on port 5. A reduced fixture based on the documented Redmi AX5400 wiring passes dtc and the complete net-next schema set. It is a binding fixture, not a bootable board port. The pinned net-next base lacks an IPQ5018 Ethernet MAC driver and an RA74 DTS description. Consequently, this series cannot demonstrate a runnable RA74 platform upstream, though this does not preclude other hardware implementations. We would appreciate review of whether this code-level qca83xx consumer is sufficient scope for the RFC while the board and MAC support remain downstream. In this revision: - Patch 3 serializes MTU updates with phylink link-up/down and port enable/disable. It restores each CPU port's original TXMAC/RXMAC state, so a link-down port stays down while LINK_AUTO is preserved. Failed status reads or MAC pauses abort before the frame-size write; restoration failures are logged even if the original operation failed. - Patch 4 defines the shared switch-to-PHY flag and marks QCA8337 internal CPU PHYs for SmartSpeed suppression. - Patch 5 consumes the flag in qca8337_soft_reset() and before the resume BMCR reset. It clears enable and bypass-timer bits, preserves other register bits and returns an MDIO error without issuing the reset. Validation: - All five exported patches pass checkpatch --strict and git mailinfo; each parsed commit message retains its DCO sign-off. Independent sequential application reproduces the tree. - ASan and UBSan function-model suites pass 7,189 CPU-selection, MDIO and MTU cases plus four resume cases, with 14 negative controls. - The current qca8k-common.o, qca8k-8xxx.o and qca83xx.o pass x86_64 and ARM64 allyesconfig/allmodconfig W=1 builds without KCFLAGS overrides. - Physical hardware testing on upstream net-next has not been performed due to the absence of upstream IPQ5018 MAC driver and board DTS. Changes from v1: - Clarified that qca83xx is already present upstream; patch 5 provides the SmartSpeed flag consumer. - Added internal CPU-PHY support (retaining Ziyang Huang's authorship). - Serialized MTU reconfiguration with MAC link-state changes and restored each port's original TXMAC/RXMAC bits while preserving LINK_AUTO. - Narrowed MDIO address filtering to preserve external user-port behavior. Original RFC: https://lore.kernel.org/netdev/20260919085406.1395-1-yongzhao.derek@gmail.com/ Maintainer response: https://lore.kernel.org/netdev/59975387-5539-47e7-bcca-4a5ed0a84bad@lunn.ch/ Yongzhao Chen (4): net: dsa: pass PHY flags when connecting shared ports net: dsa: qca8k: serialize CPU MAC pause during MTU changes net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs Ziyang Huang (1): net: dsa: qca8k: support an internal PHY as the CPU port Documentation/networking/dsa/dsa.rst | 2 + MAINTAINERS | 1 + drivers/net/dsa/bcm_sf2.c | 4 ++ drivers/net/dsa/microchip/ksz8.c | 4 ++ drivers/net/dsa/qca/qca8k-8xxx.c | 37 ++++++++++------- drivers/net/dsa/qca/qca8k-common.c | 79 +++++++++++++++++++++++++++++------- drivers/net/dsa/qca/qca8k.h | 2 + drivers/net/phy/qcom/qca83xx.c | 32 +++++++++++++-- include/linux/qca83xx.h | 11 ++++++ net/dsa/port.c | 6 ++- 10 files changed, 144 insertions(+), 34 deletions(-) create mode 100644 include/linux/qca83xx.h base-commit: 8830e65ed46de41f849eefb8ba227d4852c460f6 -- 2.43.0