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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c6f5asm11080466b.15.2026.09.22.13.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 13:27:07 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, ansuelsmth@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, florian.fainelli@broadcom.com, jonas.gorski@gmail.com, woojung.huh@microchip.com, UNGLinuxDriver@microchip.com, hzyitc@outlook.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, Yongzhao Chen Subject: [RFC PATCH net-next v2 2/5] net: dsa: qca8k: support an internal PHY as the CPU port Date: Tue, 22 Sep 2026 22:26:50 +0200 Message-ID: <20260922202653.1153-3-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260922202653.1153-1-yongzhao.derek@gmail.com> References: <20260922202653.1153-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Ziyang Huang A PHY-to-PHY CPU link connects the SoC PHY to an internal switch PHY. QCA8337 supports header mode on these ports, and the existing phylink callbacks already support their internal interfaces. Allow CPU port selection to find ports 1 through 5 after checking the MAC-only ports. Include internal CPU PHYs when deciding how to access the PHYs, without changing the treatment of MAC-only or user ports. This supports a single internal CPU PHY with an explicit phy-handle and phy-mode = "internal". The conduit uses its own PHY at the other end of the MDI connection. Existing single-CPU forwarding then uses the selected port for flooding and port membership without additional routing changes. Adapted from the OpenWrt PHY-to-PHY CPU link patch; narrow the MDIO filter change to retain existing external user-port handling. [yongzhao: preserve external user-port handling on port 6] Assisted-by: LLM Signed-off-by: Ziyang Huang Signed-off-by: Yongzhao Chen --- drivers/net/dsa/qca/qca8k-8xxx.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c index 60f2a615a..17704cb53 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1014,7 +1014,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return ret; } - if (!dsa_is_user_port(priv->ds, reg)) + if (!dsa_is_user_port(priv->ds, reg) && + !(reg > 0 && reg < 6 && dsa_is_cpu_port(priv->ds, reg))) continue; of_get_phy_mode(port, &mode); @@ -1089,17 +1090,19 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) static int qca8k_find_cpu_port(struct dsa_switch *ds) { - struct qca8k_priv *priv = ds->priv; + int port; - /* Find the connected cpu port. Valid port are 0 or 6 */ if (dsa_is_cpu_port(ds, 0)) return 0; - dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); - if (dsa_is_cpu_port(ds, 6)) return 6; + /* An internal PHY can provide a PHY-to-PHY CPU link. */ + for (port = 1; port < 6; port++) + if (dsa_is_cpu_port(ds, port)) + return port; + return -EINVAL; } @@ -1849,7 +1852,7 @@ qca8k_setup(struct dsa_switch *ds) cpu_port = qca8k_find_cpu_port(ds); if (cpu_port < 0) { - dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); + dev_err(priv->dev, "No CPU port configured"); return cpu_port; } -- 2.43.0