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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c6f5asm11080466b.15.2026.09.22.13.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 13:27:10 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, ansuelsmth@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, florian.fainelli@broadcom.com, jonas.gorski@gmail.com, woojung.huh@microchip.com, UNGLinuxDriver@microchip.com, hzyitc@outlook.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, Yongzhao Chen Subject: [RFC PATCH net-next v2 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed Date: Tue, 22 Sep 2026 22:26:52 +0200 Message-ID: <20260922202653.1153-5-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260922202653.1153-1-yongzhao.derek@gmail.com> References: <20260922202653.1153-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Mark QCA8337 internal PHYs used as CPU links for SmartSpeed suppression. These links can wait for the conduit PHY during boot, causing SmartSpeed to remove Gigabit advertisement before the conduit starts. Use a shared switch-to-PHY flag definition, preserving the revision bits already consumed by the PHY driver. Only QCA8337 CPU ports 1 through 5 receive the new flag; MAC-only ports and other roles do not. Assisted-by: LLM Signed-off-by: Yongzhao Chen --- MAINTAINERS | 1 + drivers/net/dsa/qca/qca8k-8xxx.c | 19 ++++++++++--------- drivers/net/phy/qcom/qca83xx.c | 3 +-- include/linux/qca83xx.h | 11 +++++++++++ 4 files changed, 23 insertions(+), 11 deletions(-) create mode 100644 include/linux/qca83xx.h diff --git a/MAINTAINERS b/MAINTAINERS index df8ab9b82..fa1da8031 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22336,6 +22336,7 @@ L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/dsa/qca8k.yaml F: drivers/net/dsa/qca/qca8k* +F: include/linux/qca83xx.h F: net/dsa/tag_qca.c QUALCOMM ATHEROS QCA7K ETHERNET DRIVER diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c index 787f30495..4ed1ce660 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -1744,17 +1745,17 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data) static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) { struct qca8k_priv *priv = ds->priv; + u32 flags; - /* Communicate to the phy internal driver the switch revision. - * Based on the switch revision different values needs to be - * set to the dbg and mmd reg on the phy. - * The first 2 bit are used to communicate the switch revision - * to the phy driver. - */ - if (port > 0 && port < 6) - return priv->switch_revision; + if (port <= 0 || port >= 6) + return 0; - return 0; + /* The PHY driver uses the switch revision for analog initialization. */ + flags = priv->switch_revision; + if (priv->switch_id == QCA8K_ID_QCA8337 && dsa_is_cpu_port(ds, port)) + flags |= QCA8K_DEVFLAGS_NO_SMARTSPEED; + + return flags; } static enum dsa_tag_protocol diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c index bc70ed8ef..0f484cdfe 100644 --- a/drivers/net/phy/qcom/qca83xx.c +++ b/drivers/net/phy/qcom/qca83xx.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include +#include #include #include "qcom.h" @@ -16,8 +17,6 @@ #define QCA8327_B_PHY_ID 0x004dd034 #define QCA8337_PHY_ID 0x004dd036 -#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) - static struct at803x_hw_stat qca83xx_hw_stats[] = { { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, diff --git a/include/linux/qca83xx.h b/include/linux/qca83xx.h new file mode 100644 index 000000000..f90ed80fb --- /dev/null +++ b/include/linux/qca83xx.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _LINUX_QCA83XX_H +#define _LINUX_QCA83XX_H + +#include + +/* QCA8K switch-to-PHY flags, carried through phy_device::dev_flags. */ +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) +#define QCA8K_DEVFLAGS_NO_SMARTSPEED BIT(3) + +#endif -- 2.43.0