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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c6f5asm11080466b.15.2026.09.22.13.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 13:27:11 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, ansuelsmth@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, florian.fainelli@broadcom.com, jonas.gorski@gmail.com, woojung.huh@microchip.com, UNGLinuxDriver@microchip.com, hzyitc@outlook.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, Yongzhao Chen Subject: [RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs Date: Tue, 22 Sep 2026 22:26:53 +0200 Message-ID: <20260922202653.1153-6-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260922202653.1153-1-yongzhao.derek@gmail.com> References: <20260922202653.1153-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Consume the qca8k flag on QCA8337 by clearing SmartSpeed enable and bypass-timer bits before genphy_soft_reset(). Read-modify-write preserves the remaining register bits, and a failed update prevents reset. The same clear runs before the resume BMCR reset. If MDIO access fails, resume returns the error without issuing that reset. The downstream Redmi AX5400 experiment observed Gigabit advertisement being removed while the conduit was not yet running. Applying this sequence before the initial reset preserved advertisement in that experiment. This series does not add the board support used there. Unflagged QCA8337 PHYs retain their reset sequence. QCA8327 drivers continue to use genphy_soft_reset() directly. Link: https://github.com/openwrt/openwrt/issues/24696 Assisted-by: LLM Signed-off-by: Yongzhao Chen --- drivers/net/phy/qcom/qca83xx.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c index 0f484cdfe..21ab015f6 100644 --- a/drivers/net/phy/qcom/qca83xx.c +++ b/drivers/net/phy/qcom/qca83xx.c @@ -91,6 +91,28 @@ static int qca83xx_probe(struct phy_device *phydev) return 0; } +static int qca8337_disable_smartspeed(struct phy_device *phydev) +{ + if (!(phydev->dev_flags & QCA8K_DEVFLAGS_NO_SMARTSPEED)) + return 0; + + /* SmartSpeed settings take effect at software reset. */ + return phy_clear_bits(phydev, AT803X_SMART_SPEED, + AT803X_SMART_SPEED_ENABLE | + AT803X_SMART_SPEED_BYPASS_TIMER); +} + +static int qca8337_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret = qca8337_disable_smartspeed(phydev); + if (ret) + return ret; + + return genphy_soft_reset(phydev); +} + static int qca83xx_config_init(struct phy_device *phydev) { u8 switch_revision; @@ -160,6 +182,11 @@ static int qca83xx_resume(struct phy_device *phydev) /* Reinit the port, reset values set by suspend */ qca83xx_config_init(phydev); + /* Reapply the CPU PHY quirk before the resume reset. */ + ret = qca8337_disable_smartspeed(phydev); + if (ret) + return ret; + /* Reset the port on port resume */ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); @@ -218,7 +245,7 @@ static struct phy_driver qca83xx_driver[] = { .probe = qca83xx_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, - .soft_reset = genphy_soft_reset, + .soft_reset = qca8337_soft_reset, .get_sset_count = qca83xx_get_sset_count, .get_strings = qca83xx_get_strings, .get_stats = qca83xx_get_stats, -- 2.43.0