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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Serge Semin , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi , Shawn Guo , Zhangfei Gao , Jitendra Vegiraju , Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790125674; l=7650; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=ec5frk+YtDQMLnumPZGZWsIFPqUU4OVg7LaYLxO10tQ=; b=Oe2dGKX5HImnogO3tEsFXNOVtvfzBGrsRPstHAhtUaSNg2Y/WyV5elH2n/DazKr0XJ9avzejN NzAt93U2jOAD2PcZlv9wQDR54sdI4vmZyVYij5lJIyA/l013If1HqL/ X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-GUID: VgxpfMuSsjK_Z46Fi2bpJlywrQtbBwwc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfXyUJWoYeYi2C5 dweZ1gxWc86eOCdQVAvdNPAkuhWQ8Xn0UZFeKulpzhKSK1bD+LTafDwkRKC80ceed4GRqWrm3rt 4+lB2VWJzcB9V3E1fTabShcmPKNcs/ulQNQewx9toIRu8ULQBZ2lXTviF+XXmHkguo7anRTzCBI S5W67Ue/b3O/IEmXbzqvyKPG2M8UcZDCEWlnPuctBiGwQ2KX6S3H2S35PFej3VEQ51Vv8hNr5KX 5VmJtBeDeCYbvHdsDegd3rD9SSfW6HsskjHsNQb28Do/tFjnSaw1wskv2s7wZxEhIYSjkHKR0h0 +TV+5QE70eq/HjjKKzmbkjOUUtGrzXYfsXk5y2MZ3RMyQ3jbzv3GLTEdfocXzmJXF/WnyqnDXWx zE1XrMAbGqusIt6cwcRrQS+tA+4JPix69oDiyn+R+/TDnSACjd0+MYr9uG77ssHPVzIRapa2QYN /pU2XN13utXKjfOPqdg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAwNCBTYWx0ZWRfX1TDqpCSrtBg9 7KqC8cVD13m8tbiCDZGf+rhokdfCI8hCyidBwnPnUQlG7g+5RzXmmQWEqDG42AQFwPrfsjm/rbz yhBxZFz6yh2NNq/GTDtkj2RNiDfRjWM= X-Authority-Analysis: v=2.4 cv=QsDLTlyd c=1 sm=1 tr=0 ts=6ab32688 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=CxBzW-8FhjC1KXsKZjIA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: VgxpfMuSsjK_Z46Fi2bpJlywrQtbBwwc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230004 The generic DesignWare XPCS support currently associates USXGMII with Clause 73 auto-negotiation. The XPCS integration on Qualcomm Nord instead uses the vendor MII register block and Clause 37 control and status for USXGMII. Add a separate Clause 37 USXGMII mode which configures the PCS for BASE-R, enables single-port 10G-SXGMII operation and enables PHY-side Clause 37 auto-negotiation. Also decode the negotiated link, speed and duplex from the vendor Clause 37 status register. This supports 10 Mbps through 10 Gbps link rates exposed by the USXGMII status fields. Signed-off-by: Mohd Ayaan Anwar --- drivers/net/pcs/pcs-xpcs.c | 113 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/pcs/pcs-xpcs.h | 15 ++++++ include/linux/pcs/pcs-xpcs.h | 1 + 3 files changed, 129 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 0337e2bcc01258e102a649e3b7fce41c65a3dd05..7f5c7a275630f2b064e4b9abdd6c3619e9346cec 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -283,6 +283,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, switch (compat->an_mode) { case DW_AN_C73: case DW_10GBASER: + case DW_AN_C37_USXGMII: dev = MDIO_MMD_PCS; break; case DW_AN_C37_SGMII: @@ -355,6 +356,54 @@ static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, return 0; } +static int xpcs_config_aneg_c37_usxgmii(struct dw_xpcs *xpcs) +{ + u16 mask, val; + int ret; + + /* Select BASE-R PCS mode. */ + ret = xpcs_modify(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, + DW_PCS_TYPE_SEL, MDIO_PCS_CTRL2_10GBR); + if (ret < 0) + return ret; + + /* Enable USXGMII before accessing the MII MMD registers. */ + ret = xpcs_modify_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, + DW_USXGMII_EN, DW_USXGMII_EN); + if (ret < 0) + return ret; + + /* Select single-port 10G-SXGMII mode. */ + ret = xpcs_modify_vpcs(xpcs, DW_VR_XS_PCS_KR_CTRL, + DW_USXG_MODE_SEL, + FIELD_PREP(DW_USXG_MODE_SEL, + DW_USXG_MODE_10G_SXGMII)); + if (ret < 0) + return ret; + + /* Disable Clause 37 AN before changing its configuration. */ + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_ANENABLE, 0); + if (ret < 0) + return ret; + + /* Configure USXGMII per XPCS databook section 7.6. */ + mask = DW_VR_MII_AN_CTRL_8BIT | DW_VR_MII_SGMII_LINK_STS | + DW_VR_MII_TX_CONFIG_MASK | DW_VR_MII_PCS_MODE_MASK | + DW_VR_MII_AN_INTR_EN; + val = FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, + DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII) | + DW_VR_MII_SGMII_LINK_STS; + + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, + mask, val); + if (ret < 0) + return ret; + + return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_ANENABLE, BMCR_ANENABLE); +} + static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) { int ret, speed_sel; @@ -687,6 +736,7 @@ static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, case DW_10GBASER: case DW_2500BASEX: + case DW_AN_C37_USXGMII: return LINK_INBAND_DISABLE; default: @@ -950,6 +1000,11 @@ static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, if (ret) return ret; break; + case DW_AN_C37_USXGMII: + ret = xpcs_config_aneg_c37_usxgmii(xpcs); + if (ret) + return ret; + break; case DW_2500BASEX: ret = xpcs_config_2500basex(xpcs); if (ret) @@ -1158,6 +1213,58 @@ static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, return 0; } +static int xpcs_get_state_c37_usxgmii(struct dw_xpcs *xpcs, + struct phylink_link_state *state) +{ + u16 speed; + int ret; + + state->link = false; + state->an_complete = false; + state->speed = SPEED_UNKNOWN; + state->duplex = DUPLEX_UNKNOWN; + state->pause = 0; + + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); + if (ret < 0) + return ret; + + state->an_complete = !!(ret & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR); + state->link = !!(ret & DW_VR_MII_USXG_LINK); + if (!state->link) + return 0; + + speed = FIELD_GET(DW_VR_MII_USXG_SPEED, ret); + switch (speed) { + case DW_VR_MII_USXG_SPEED_10: + state->speed = SPEED_10; + break; + case DW_VR_MII_USXG_SPEED_100: + state->speed = SPEED_100; + break; + case DW_VR_MII_USXG_SPEED_1000: + state->speed = SPEED_1000; + break; + case DW_VR_MII_USXG_SPEED_10000: + state->speed = SPEED_10000; + break; + case DW_VR_MII_USXG_SPEED_2500: + state->speed = SPEED_2500; + break; + case DW_VR_MII_USXG_SPEED_5000: + state->speed = SPEED_5000; + break; + default: + state->link = false; + return 0; + } + + state->duplex = ret & DW_VR_MII_USXG_FULL ? + DUPLEX_FULL : DUPLEX_HALF; + + return 0; +} + static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) { @@ -1191,6 +1298,12 @@ static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); break; + case DW_AN_C37_USXGMII: + ret = xpcs_get_state_c37_usxgmii(xpcs, state); + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_c37_usxgmii", ERR_PTR(ret)); + break; case DW_2500BASEX: ret = xpcs_get_state_2500basex(xpcs, state); if (ret) diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 929fa238445ed550677850b9b89149e952ac9fd6..cbf583ff55ba0884efb9c8b63a07154628ee5ea2 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -13,6 +13,7 @@ #define DW_VENDOR BIT(15) /* VR_XS_PCS */ +#define DW_PCS_TYPE_SEL GENMASK(3, 0) #define DW_USXGMII_RST BIT(10) #define DW_USXGMII_EN BIT(9) #define DW_VR_XS_PCS_DIG_CTRL1 0x0000 @@ -20,6 +21,9 @@ #define DW_EN_VSMMD1 BIT(13) #define DW_CL37_BP BIT(12) #define DW_VR_XS_PCS_DIG_STS 0x0010 +#define DW_VR_XS_PCS_KR_CTRL 0x0007 +#define DW_USXG_MODE_SEL GENMASK(12, 10) +#define DW_USXG_MODE_10G_SXGMII 0 #define DW_RXFIFO_ERR GENMASK(6, 5) #define DW_PSEQ_ST GENMASK(4, 2) #define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4) @@ -68,6 +72,7 @@ #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 #define DW_VR_MII_AN_INTR_EN BIT(0) +#define DW_VR_MII_SGMII_LINK_STS BIT(4) #define DW_VR_MII_AN_INTR_STS 0x8002 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0) @@ -78,6 +83,16 @@ #define DW_VR_MII_C37_ANSGM_SP_1000 0x2 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4) +#define DW_VR_MII_USXG_LINK BIT(14) +#define DW_VR_MII_USXG_FULL BIT(13) +#define DW_VR_MII_USXG_SPEED GENMASK(12, 10) +#define DW_VR_MII_USXG_SPEED_10 0 +#define DW_VR_MII_USXG_SPEED_100 1 +#define DW_VR_MII_USXG_SPEED_1000 2 +#define DW_VR_MII_USXG_SPEED_10000 3 +#define DW_VR_MII_USXG_SPEED_2500 4 +#define DW_VR_MII_USXG_SPEED_5000 5 + #define DW_VR_MII_EEE_MCTRL0 0x8006 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */ #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */ diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h index 36073f7b6bb40e02c523112f79b3c55838a778e2..4ea995b70150e33e1e1a47cc7aa324c53742fbdc 100644 --- a/include/linux/pcs/pcs-xpcs.h +++ b/include/linux/pcs/pcs-xpcs.h @@ -20,6 +20,7 @@ #define DW_2500BASEX 3 #define DW_AN_C37_1000BASEX 4 #define DW_10GBASER 5 +#define DW_AN_C37_USXGMII 6 enum dw_xpcs_pcs_id { DW_XPCS_ID_NATIVE = 0, -- 2.34.1