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[83.233.130.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae6dcf0dsm197647666b.61.2026.09.23.14.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 14:59:17 -0700 (PDT) From: Yongzhao Chen To: netdev@vger.kernel.org Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Russell King , linux-kernel@vger.kernel.org, Ziyang Huang Subject: [RFC PATCH net-next v3 3/5] net: dsa: qca8k: support QCA8337 internal PHY CPU links Date: Wed, 23 Sep 2026 23:58:55 +0200 Message-ID: <20260923215858.1653-4-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260923215858.1653-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Ziyang Huang A PHY-to-PHY CPU link connects the SoC PHY directly to an internal switch PHY. The QCA8337 supports header mode on these ports, and existing phylink callbacks already handle their internal interfaces. Allow QCA8337 CPU port selection to fall back to ports 1 through 5 after checking the dedicated MAC-only ports. Preserve the preference for CPU ports 0 and 6 across all switch models, limiting the internal-port fallback to QCA8337. Support for QCA8327 internal CPU links remains an open question in this RFC. Include internal CPU PHYs when selecting the PHY access method, without altering the handling of MAC-only or external user ports. This enables a single internal CPU PHY configured with an explicit phy-handle and phy-mode = "internal". The conduit interface uses its own PHY on the opposite side of the MDI connection. Existing single-CPU DSA forwarding uses the selected port for default flooding and membership without extra routing changes. Adapted from the OpenWrt PHY-to-PHY CPU link patch, narrowing the MDIO filter adjustments to preserve handling for external user ports. [yongzhao: preserve external user-port handling on port 6 and limit internal CPU PHY support to QCA8337] Assisted-by: LLM Signed-off-by: Ziyang Huang Signed-off-by: Yongzhao Chen --- drivers/net/dsa/qca/qca8k-8xxx.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c index d8564001c..07640ce4a 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1019,7 +1019,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return ret; } - if (!dsa_is_user_port(priv->ds, reg)) + if (!dsa_is_user_port(priv->ds, reg) && + !(reg > 0 && reg < 6 && dsa_is_cpu_port(priv->ds, reg))) continue; of_get_phy_mode(port, &mode); @@ -1095,16 +1096,23 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) static int qca8k_find_cpu_port(struct dsa_switch *ds) { struct qca8k_priv *priv = ds->priv; + int port; - /* Find the connected cpu port. Valid port are 0 or 6 */ if (dsa_is_cpu_port(ds, 0)) return 0; - dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); - if (dsa_is_cpu_port(ds, 6)) return 6; + /* Internal PHY CPU port selection is currently enabled for QCA8337. */ + if (priv->switch_id != QCA8K_ID_QCA8337) + return -EINVAL; + + /* An internal PHY can provide a PHY-to-PHY CPU link. */ + for (port = 1; port < 6; port++) + if (dsa_is_cpu_port(ds, port)) + return port; + return -EINVAL; } @@ -1856,7 +1864,7 @@ qca8k_setup(struct dsa_switch *ds) cpu_port = qca8k_find_cpu_port(ds); if (cpu_port < 0) { - dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); + dev_err(priv->dev, "No CPU port configured"); return cpu_port; } -- 2.43.0