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[83.233.221.53]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2ae7353f0asm274704166b.15.2026.09.26.14.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2026 14:52:05 -0700 (PDT) From: Yongzhao Chen To: Andrew Lunn Cc: netdev@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Vladimir Oltean , Christian Marangi , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Ziyang Huang Subject: Re: [RFC PATCH net-next v3 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed Date: Sat, 26 Sep 2026 23:51:52 +0200 Message-ID: <20260926215152.376-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <426f9dcb-7473-48d5-a473-4435cc81312c@lunn.ch> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> <20260923215858.1653-5-yongzhao.derek@gmail.com> <09d669ff-7aad-4414-880a-21c2e7bf2cd7@lunn.ch> <20260924234814.1734-1-yongzhao.derek@gmail.com> <20260925210153.8717-1-yongzhao.derek@gmail.com> <69b36e16-eece-4739-9208-96bd8e60943f@lunn.ch> <20260926082129.1632-1-yongzhao.derek@gmail.com> <426f9dcb-7473-48d5-a473-4435cc81312c@lunn.ch> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Andrew, > The IPQ5018 PHY driver does have cable test support, have you tried it > out? Yes. I ran it seven times on the IPQ5018 PHY under OpenWrt 6.18.44 (NSS build). All four pairs reported OK each time. This was a working link, so the result does not show what the QCA8337 sees during a failed boot, or confirm or rule out insufficient attenuation. I also ran an A/B test on the OpenWrt 6.18.52 backport, using identical kernel and rootfs contents. Before the initial PHY software reset, both paths read register 0x14 once and unconditionally wrote it once: either the original value, or the value with SmartSpeed disabled. Across six alternating warm boots on this board: - Writing back 0x082c failed all three times. PHY4's CTRL1000 read 0x0400, register 0x11 read 0x1030, and the CPU link did not come up. - Writing 0x080c worked all three times. CTRL1000 read 0x0600 and the CPU link came up at 1 Gb/s. The pre-reset value was 0x082c in every run; the two written values therefore differed only in the SmartSpeed enable bit. Writing the original value back did not avoid the failure, despite the same MDIO access sequence. This strengthens the case for disabling SmartSpeed on this link, but does not establish the electrical cause. I'm open to selecting the workaround through DT, so that it is enabled only on boards known to need it. What I can document at this point is the PHY-to-PHY connection, the reproducible boot failure and the effect of disabling SmartSpeed. I have not established whether the cause is the board's electrical design or something else. Would that be sufficient justification for a DT property, with the underlying cause left open in the commit message? If so, would you prefer a generic PHY property to disable downshift, or a Qualcomm-specific property for this workaround? Thanks, Yongzhao Chen