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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Andrew Lunn , Vladimir Oltean , Christian Marangi , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [RFC PATCH net-next v3 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed Date: Sun, 27 Sep 2026 17:35:58 +0200 Message-ID: <20260927153558.2299-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: References: <20260923215858.1653-1-yongzhao.derek@gmail.com> <20260923215858.1653-5-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Ziyang,=0D =0D > Have you correct the DAC settings of the IPQ5018 PHY ?=0D =0D Thank you for pointing this out. It turned out that the DAC values were=0D not being applied on my board.=0D =0D The OpenWrt DTS for this board sets qcom,dac-preset-short-cable, but=0D ipq5018_config_init() passes the unshifted value 0x10 to=0D phy_modify_mmd() and at803x_debug_reg_mask() while the mask is=0D GENMASK(15, 8). As a result, the high byte is cleared instead of being=0D set to 0x10, and bit 4 of the low byte is set. The same code is in=0D net-next today. All my earlier A/B runs, including the ones I reported=0D to Andrew, were done with this code. I will send the DAC fix as a=0D separate patch.=0D =0D With both writes changed to FIELD_PREP(IPQ5018_PHY_DAC_MASK, 0x10), I=0D repeated the A/B on the same board: six alternating warm boots with=0D identical kernel and rootfs contents. The only difference between the=0D two groups was whether SmartSpeed on the QCA8337 CPU PHY was left=0D enabled or disabled before its initial reset. I kept 0x10 and did not=0D try other values, given your warning. In all six boots the read-back=0D after the write was MDAC 0x6868 -> 0x1068 and EDAC 0x7800 -> 0x1000,=0D so the high byte was 0x10 and the low byte was preserved.=0D =0D The result was the same as before:=0D =0D - SmartSpeed left enabled: failed 3/3. PHY4's CTRL1000 read 0x0400,=0D register 0x11 read 0x1030, and the CPU link did not come up.=0D - SmartSpeed disabled: 3/3 came up at 1 Gb/s.=0D =0D So correcting the DAC values alone did not avoid the failure in this=0D setup. I don't think this rules the DAC out yet, though, because of the=0D ordering. In these boots the QCA8337 CPU PHY (PHY4) was reset at about=0D 2.3 s, while the IPQ5018 PHY's config_init(), which writes the DAC=0D values, ran at about 40 s. For roughly 38 s PHY4 may have been=0D negotiating with an IPQ5018 PHY that still had its reset-default DAC=0D values. I have not yet measured when PHY4 first drops its 1000BASE-T=0D advertisement relative to the DAC write.=0D =0D Do you know whether the vendor code has an ordering requirement here,=0D for example setting the IPQ5018 DAC before the switch-side PHY starts=0D autonegotiation, or restarting the link after the DAC has been set?=0D Any pointer would be much appreciated.=0D =0D Thanks,=0D Yongzhao Chen=0D