From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BDE8511E76; Mon, 28 Sep 2026 19:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790624038; cv=none; b=BPJjb4b3SKwjGYOD35h15opvSh88eZAUFjQ61vhJueAQEvDhwwLabPaJzMqBr8SrlIlf+13nH20yqmFt2MaQG2QMoIpR9nwZefDAxerW5sYwVBubor0t+MpT89dHSLFTojc3d/Z/kwY0DGRh+Y6H/a3INzIFlZ7ORNoNagAmXP8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790624038; c=relaxed/simple; bh=c5Izg07tkdc5eWh/EbdJlKt5hNZ4OwsKWgWyQGIZoTY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=UhIXwXkyu7m+fplod1GozAEOPOx9/YuDEZG08X+raZEcDIqoU99nyxrfRbzOAVRq5+vW5pYzkrNjrb54kxcewAX9k6lKsI9bZuux6vsKrZi878vVz4S8Atv9vK81zlt74E9WtlQDlDsjGWRNG9nEVl65R44HJhWKZZCFBWqnBI0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=powXOAwR; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="powXOAwR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1790624038; x=1822160038; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=c5Izg07tkdc5eWh/EbdJlKt5hNZ4OwsKWgWyQGIZoTY=; b=powXOAwROakFFf0J6ImmXbOl9HHkj+0p+TkDOnJZhxMgUQpLQIGiItLX qDvlF+pT8MUKPrWRBmQtBS/zZkmrKXt8tmd58xqe+fp9/ej/flhCd1uo6 La19mE/IkV5cRz0pm1MfjjrLPXyymlDUjfhp0WowDhq2eZEqxqwr5h8ZU G2065wQv8O2C/5ISzcmLxiyJxen7YbyspIs+mEff4/lj/aOMEHmTy1Dce jo11LfRibI7Fr8uY3+WStc0s0IErYP1HwxyF60LZeAAi67hbba/Rf2Clm qYgOFTn0gtp7F4znoqCeBp3LShSBlVlfAOl2q17Ub4QHonR8cAumWjsYw A==; X-CSE-ConnectionGUID: PmIgluTtSYiIzqow5MRFoQ== X-CSE-MsgGUID: l0f6BRqzRz+ZT+LGz5PRtg== X-IronPort-AV: E=Sophos;i="6.27,129,1787036400"; d="scan'208";a="64282792" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2026 12:33:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Mon, 28 Sep 2026 12:33:55 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 28 Sep 2026 12:33:51 -0700 From: Daniel Machon Date: Mon, 28 Sep 2026 21:33:02 +0200 Subject: [PATCH net-next v9 14/15] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260928-lan966x-pci-fdma-v9-14-a17caf60f89a@microchip.com> References: <20260928-lan966x-pci-fdma-v9-0-a17caf60f89a@microchip.com> In-Reply-To: <20260928-lan966x-pci-fdma-v9-0-a17caf60f89a@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir , "Simon Horman" CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, + reg = <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; -- 2.34.1