From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BD564FDE71; Mon, 28 Sep 2026 19:33:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790624001; cv=none; b=M6zT48vSsc2OpGTMmqUwBSvOMo+cUrX7RruE73Tmsr7AxNHJGCiG4s1c4OnozsJWt70Saxs8UpvT2bxOya/etWOdvFOoD9VH90YxHOywVkz6ZlIXJ9I6hT+kz72vJTrUPbZEZ8oLEnUfirxgehWaDvuawTDpst0woaYEyiRxmC8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790624001; c=relaxed/simple; bh=bTmIpqNrNvU3IHtPezg+HL5Y1+Y1opzwgINLmoX0OYI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=be+l5xZrcCvoNi0lgfA5pVpGS9tXS5HeLcB3cnYZHgzYtnx+SfAFUImh6jsWMwRkih3bo25zbdA6XXbbmuq3HEQP+reBmUKXOKlbVOY86lwaBDZUHkS3lsv/lHEXwL706PyiM/lLiQj7K68GPwAypFb8xEoLj/gdANeut4BljMI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=yX6Ytk6f; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="yX6Ytk6f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1790624004; x=1822160004; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=bTmIpqNrNvU3IHtPezg+HL5Y1+Y1opzwgINLmoX0OYI=; b=yX6Ytk6fMgSLs7TsNL9GYn2n3yPwcsHKkngdLuVFE38pspb5La7JxqDZ /7KvX6Uu6HGqWJ0mwpqYxTiKRwHC8WRe1gQK5Ag51thUXlmSadTKRJ8op ZzqMMWaTyQiErWiK1bl3soYT1Vcns0w129grv9XUNGdtCjRJmOYM0O0Gb uO+uugAw+7hOphNy/R6oE0HEwf3ZtzTDWCfMUmoS39EWowYHa+Sq0qogx WSdtYNhaZWIAbhDpGpkCta7kyufqdHwq/Q0ktdXzQwpHh1imsBYL01ASZ wFa5xgTKYixw+nd/Mhuw7CEUdVXIoiI232sQVF7AAnlYzISn3v0jNt3we Q==; X-CSE-ConnectionGUID: zmhlKOivQ1yDqUVw/y1OBQ== X-CSE-MsgGUID: z2YCpmweTciR2b814+J5gA== X-IronPort-AV: E=Sophos;i="6.27,129,1787036400"; d="scan'208";a="64576547" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Sep 2026 12:33:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 28 Sep 2026 12:33:18 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 28 Sep 2026 12:33:14 -0700 From: Daniel Machon Date: Mon, 28 Sep 2026 21:32:53 +0200 Subject: [PATCH net-next v9 05/15] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260928-lan966x-pci-fdma-v9-5-a17caf60f89a@microchip.com> References: <20260928-lan966x-pci-fdma-v9-0-a17caf60f89a@microchip.com> In-Reply-To: <20260928-lan966x-pci-fdma-v9-0-a17caf60f89a@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir , "Simon Horman" CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 ++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c index 68fd454ebc98..1c5484a506ff 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,6 +109,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan966x_rx *rx) return 0; } +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x = rx->lan966x; @@ -128,6 +135,8 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; } @@ -137,14 +146,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) struct fdma *fdma = &rx->fdma; u32 mask; - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -215,6 +216,8 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) fdma_dcbs_init(fdma, 0, 0); + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; out: @@ -236,14 +239,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx *tx) struct fdma *fdma = &tx->fdma; u32 mask; - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -877,6 +872,9 @@ static int lan966x_fdma_reload(struct lan966x *lan966x, int new_mtu) MEM_TYPE_PAGE_POOL, page_pool); } + lan966x_fdma_llp_configure(lan966x, lan966x->rx.fdma.dma, + lan966x->rx.fdma.channel_id); + lan966x_fdma_rx_start(&lan966x->rx); lan966x_fdma_wakeup_netdev(lan966x); -- 2.34.1