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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Vladimir Oltean , Christian Marangi , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Ziyang Huang , George Moussalem Subject: Re: [RFC PATCH net-next v3 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed Date: Mon, 28 Sep 2026 08:57:58 +0200 Message-ID: <20260928065758.5507-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20260927153616.2317-1-yongzhao.derek@gmail.com> References: <20260923215858.1653-1-yongzhao.derek@gmail.com> <20260923215858.1653-5-yongzhao.derek@gmail.com> <09d669ff-7aad-4414-880a-21c2e7bf2cd7@lunn.ch> <20260924234814.1734-1-yongzhao.derek@gmail.com> <20260925210153.8717-1-yongzhao.derek@gmail.com> <69b36e16-eece-4739-9208-96bd8e60943f@lunn.ch> <20260926082129.1632-1-yongzhao.derek@gmail.com> <426f9dcb-7473-48d5-a473-4435cc81312c@lunn.ch> <20260926215152.376-1-yongzhao.derek@gmail.com> <20260927153616.2317-1-yongzhao.derek@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Andrew,=0D =0D Following up on the initialisation order, as promised. On this board=0D it was the cause, and the DT workaround is not needed.=0D =0D The IPQ5018 GE PHY leaves reset in ipq5018_probe() and starts=0D autonegotiating with its reset defaults. Its LDO, EEE, MSE and DAC=0D settings are only written in ipq5018_config_init(), when stmmac=0D attaches the PHY on open, about 39 s later on this board. I sampled=0D both PHYs during that window. They resolved 1000BASE-T every 2.5 to 3 s=0D without getting link, and after about five attempts SmartSpeed=0D downshifted on both sides at the same moment: the IPQ5018 PHY's=0D CTRL1000 went 0x0200 -> 0x0000 and PHY4's 0x0600 -> 0x0400. The soft=0D reset at attach restores the IPQ5018 side, but nothing touches PHY4=0D again, so the CPU link never came up.=0D =0D Applying the same analog settings in probe, right after the reset, and=0D restarting autonegotiation, fixed it with SmartSpeed left enabled on=0D the QCA8337: 3 of 3 warm boots came up at 1 Gb/s about 2.5 s after PHY4=0D was reset, against 0 of 3 without it. Both groups ran the same kernel=0D and rootfs, with the probe-time writes enabled by a private DT property.=0D The final patch was then checked on the same board over a first boot,=0D three reboots, three interface down/up cycles, three renegotiations, a=0D network restart and a 10 minute observation, all at 1 Gb/s with=0D SmartSpeed enabled. It is still one board, and I have not done a=0D power-cycle test on this kernel.=0D =0D So I will not add the workaround property. I will send the at803x=0D change to net together with the DAC fix, and v4 of this series without=0D patches 4 and 5. George, I've Cc'd you since the at803x change touches=0D the IPQ5018 probe path you added.=0D =0D Thanks,=0D Yongzhao=0D