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Mon, 28 Sep 2026 19:33:16 +0000 (UTC) From: Marc Kleine-Budde To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, linux-can@vger.kernel.org, kernel@pengutronix.de, Maximilian Zimmermann , stable@vger.kernel.org, Marc Kleine-Budde Subject: [PATCH net 14/22] can: xilinx_can: set CAN FD flags on received frames Date: Mon, 28 Sep 2026 20:45:21 +0200 Message-ID: <20260928193312.553632-15-mkl@pengutronix.de> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260928193312.553632-1-mkl@pengutronix.de> References: <20260928193312.553632-1-mkl@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Maximilian Zimmermann The Xilinx CAN FD controller reports the bit rate switch (BRS) and error state indicator (ESI) in the receive buffer DLC register. The receive path currently uses this register to determine frame format and payload length, but does not set BRS and ESI in struct canfd_frame::flags. This results in applications being unable to receive the BRS and ESI flags, even when the controller correctly received them. Add the ESI register mask and copy the controller flags to the corresponding SocketCAN canfd_frame struct. Fixes: c223da689324 ("can: xilinx_can: Add support for CANFD FD frames") Cc: stable@vger.kernel.org Signed-off-by: Maximilian Zimmermann Link: https://patch.msgid.link/20260921-fix-xilinx-canfd-flags-v1-1-a371c90b4e7c@spacecubics.com Signed-off-by: Marc Kleine-Budde --- drivers/net/can/xilinx_can.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index 43d7f22820b8..52661e088205 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -157,6 +157,7 @@ enum xcan_reg { #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ +#define XCAN_DLCR_ESI_MASK 0x02000000 /* ESI Mask in DLC */ #define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counters */ #define XCAN_ECC_CFG_REECTXOL_MASK BIT(1) /* Reset TXOL FIFO ECC error counters */ #define XCAN_ECC_CFG_REECTXTL_MASK BIT(0) /* Reset TXTL FIFO ECC error counters */ @@ -959,6 +960,11 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base) /* Check the frame received is FD or not*/ if (dlc & XCAN_DLCR_EDL_MASK) { + if (dlc & XCAN_DLCR_BRS_MASK) + cf->flags |= CANFD_BRS; + if (dlc & XCAN_DLCR_ESI_MASK) + cf->flags |= CANFD_ESI; + for (i = 0; i < cf->len; i += 4) { dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) + (dwindex * XCANFD_DW_BYTES); -- 2.53.0