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Mon, 28 Sep 2026 15:09:16 -0700 (PDT) Received: from localhost.localdomain ([2a00:801:793:68fd:c07a:9093:1956:b4bf]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2ae7352336sm533842866b.16.2026.09.28.15.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 15:09:16 -0700 (PDT) From: Yongzhao Chen To: netdev-bot+sashiko@kernel.org Cc: netdev@vger.kernel.org, ansuelsmth@gmail.com, andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH net] net: dsa: qca8k: propagate MDIO errors Date: Tue, 29 Sep 2026 00:08:58 +0200 Message-ID: <20260928220858.1982-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <179054715863.3145.10179961093285192493@kernel.org> References: <20260923215748.1336-1-yongzhao.derek@gmail.com> <179054715863.3145.10179961093285192493@kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Sun, 27 Sep 2026 22:12:38 +0000, Sashiko wrote: > qca8k_mdio_read() has the same pattern. Could a set_page failure unlock > and return directly, or use a separate label, so that the MASTER_EN > clear only runs after page 0 has been selected? Yes. No transaction has started at that point, so there is nothing to clean up, and the write can hit a register on another page. The next version returns right after a failed page select. It also invalidates the cached page, since a failed page write may still have reached the switch. > Doesn't the same outcome remain on this Ethernet path? Should the check > after read_poll_timeout() in qca8k_phy_eth_command() also bail out when > ret < 0 and ret1 == 0? Yes. The next version stops polling on the first failed request and returns the poll error or the timeout, so qca8k_internal_mdio_read() falls back to the MDIO bus. The same exit path also leaked read_skb; that is fixed too. Both problems predate this patch. I reproduced them with a userspace model that compiles the driver's own functions. My board (QCA8337 with its PHYs on the SoC MDIO bus and no CPU port 0) never uses these paths, so they are not hardware-tested. v2 will be a three-patch series with one patch per issue. pw-bot: cr Thanks, Yongzhao