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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 3/6] net: stmmac: dwmac-meson8b: add support for the Amlogic T7 Date: Sun, 4 Oct 2026 15:40:43 +0100 Message-ID: <20261004144046.391444-4-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261004144046.391444-1-tanure@linux.com> References: <20261004144046.391444-1-tanure@linux.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The glue registers on the T7 are laid out exactly as the G12A ones, RX delay field included, so the T7 can reuse the G12A settings. What the T7 does not share is how the controller reaches DRAM: the bus path goes through a pipeline stage with a gate of its own, and no device other than the controller has any use for that gate. Claim it and hold it enabled for as long as the controller is bound, otherwise it is switched off as unused and a transfer that has been started can never complete. Give the T7 match data of its own so that only it looks the clock up, and require the clock instead of treating it as optional: the controller cannot do DMA without it, and failing the probe with a clear message beats booting and hitting an undiagnosable hang later. Assisted-by: LLM Signed-off-by: Lucas Tanure --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index e4d5c41294f4..450f7b4b29a6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -81,6 +81,7 @@ struct meson8b_dwmac; struct meson8b_dwmac_data { int (*set_phy_mode)(struct meson8b_dwmac *dwmac); bool has_prg_eth1_rgmii_rx_delay; + bool has_pipeline_clk; }; struct meson8b_dwmac { @@ -384,6 +385,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct meson8b_dwmac *dwmac; + struct clk *pipeline_clk; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -443,6 +445,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (IS_ERR(dwmac->timing_adj_clk)) return PTR_ERR(dwmac->timing_adj_clk); + if (dwmac->data->has_pipeline_clk) { + pipeline_clk = devm_clk_get_enabled(dwmac->dev, "pipeline"); + if (IS_ERR(pipeline_clk)) + return dev_err_probe(dwmac->dev, PTR_ERR(pipeline_clk), + "missing pipeline clock\n"); + } + ret = meson8b_init_rgmii_delays(dwmac); if (ret) return ret; @@ -479,6 +488,12 @@ static const struct meson8b_dwmac_data meson_g12a_dwmac_data = { .has_prg_eth1_rgmii_rx_delay = true, }; +static const struct meson8b_dwmac_data meson_t7_dwmac_data = { + .set_phy_mode = meson_axg_set_phy_mode, + .has_prg_eth1_rgmii_rx_delay = true, + .has_pipeline_clk = true, +}; + static const struct of_device_id meson8b_dwmac_match[] = { { .compatible = "amlogic,meson8b-dwmac", @@ -500,6 +515,10 @@ static const struct of_device_id meson8b_dwmac_match[] = { .compatible = "amlogic,meson-g12a-dwmac", .data = &meson_g12a_dwmac_data, }, + { + .compatible = "amlogic,t7-dwmac", + .data = &meson_t7_dwmac_data, + }, { } }; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); -- 2.56.0