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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN2PEPF000055DA.mail.protection.outlook.com (10.167.245.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.3 via Frontend Transport; Mon, 5 Oct 2026 09:01:25 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 5 Oct 2026 04:01:10 -0500 Received: from xhdharinik40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 5 Oct 2026 04:01:07 -0500 From: Kusuma Vasana To: , , , , , , , CC: , , , Subject: [PATCH net-next V4] net: axienet: Clear stale AXI DMA TX/RX status before re-enabling interrupts Date: Mon, 5 Oct 2026 14:31:06 +0530 Message-ID: <20261005090106.1594994-1-kusuma.vasana@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DA:EE_|SA3PR12MB7998:EE_ X-MS-Office365-Filtering-Correlation-Id: f5470441-6882-4fbc-c433-08df22bf3c3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|36860700016|82310400026|1800799024|10067099003|11063799006|5023799004|56012099006|18002099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ceDzd5bNlIhkbbOdcLjp1QJxsPO4/IBjtDoyFR03TR9GMP/5f6biZAkyOi/BQqXhlpihYPjnCfdlnooAunFjQ8lpg+G7AwGEUeDA0k/+qkU7A9fZJWOe3ydBZXDArK1UTeQ0UwtEiz0qbBuSrRbvHYz23gJNPfkt0xz2+KHzO3lGJmbzmx1cDeRHtPWXmeKW1EsHeI9ZWzltUlLlJF0y32QiKTkGoyXV2jn73I1Mtfd9FNsc9lwFRFy1RDSdu9GnAGWlzmXtnpF4nolLnOvcovZx9Un069V0LC2k4ojRaZaYaJ7rW1SDggc9n+3Ip9ktyqcnEIM0AW3NqfCXehu2GmA9Hkd3IBa6BbkMjlXusUcZE4PD4aF+uf7b+AGIrgAXTgo2UAmq43O1hChD90z2Gz29eBfRzsalmFs5/2rvgfbhn99OSXM1FZnLJc41/CrF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 09:01:25.4217 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5470441-6882-4fbc-c433-08df22bf3c3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7998 The AXI DMA interrupt line is level-sensitive: it asserts whenever the IOC (XAXIDMA_IRQ_IOC_MASK) or DELAY (XAXIDMA_IRQ_DELAY_MASK) bits in the status register (XAXIDMA_TX_SR_OFFSET / XAXIDMA_RX_SR_OFFSET) are set and their corresponding enable bits in the control register are active. During TX/RX, interrupts are disabled in the control register while NAPI runs. Completions arriving in this window cause hardware to latch IOC/DELAY into the status register regardless of the control register mask state. After NAPI completion, re-enabling interrupts immediately re-asserts the IRQ line due to these stale status register bits, even when no new work is pending. This results in a stale interrupt and redundant NAPI poll cycle with no new work pending, causing unnecessary CPU processing. In the initial driver, the status register was cleared after polling all packets, which naturally consumed any status accumulated during processing. In later versions of the driver, status register clearing was moved to the ISR before polling begins, leaving no mechanism to clear status bits that arrive during the NAPI poll window. Clear the status register IOC/DELAY bits before re-enabling interrupts and recheck the next BD to catch race-window completions. Both are skipped on budget exhaustion. On the RX side, both are additionally skipped on refill failure. Signed-off-by: Kusuma Vasana --- Changes in v4: - Read back SR after W1C so the clear is posted before the BD recheck. - Document that poll may return @budget on that recheck. - Drop the incorrect "leave IRQ armed" wording for RX refill failure. Changes in v3: - Updated the commit description. - Restricted TX/RX status-register clear and completion recheck to the NAPI completion path, with RX only when refill succeeds. - Rechecked descriptor completion after status-register clear to handle race-window completions. Changes in v2: -Added net-next prefix in the subject -Updated the commit description --- .../net/ethernet/xilinx/xilinx_axienet_main.c | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index fcf517069d16..4d8169fc39cd 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -986,7 +986,8 @@ axienet_start_xmit_dmaengine(struct sk_buff *skb, struct net_device *ndev) * @napi: Pointer to NAPI structure. * @budget: Max number of TX packets to process. * - * Return: Number of TX packets processed. + * Return: Number of TX packets processed, or @budget to continue polling + * after a post-clear completion recheck. * * This function is invoked from the NAPI processing to notify the completion * of transmit operation. It clears fields in the corresponding Tx BDs and @@ -1018,6 +1019,17 @@ static int axienet_tx_poll(struct napi_struct *napi, int budget) netif_wake_queue(ndev); } + /* Clear stale IOC/DELAY bits, flush the clear, and re-check for + * race-window completions. Skipped on budget exhaustion. + */ + if (packets < budget) { + axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, + XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); + axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); + if (lp->tx_bd_v[lp->tx_bd_ci].status & XAXIDMA_BD_STS_COMPLETE_MASK) + return budget; + } + if (packets < budget && napi_complete_done(napi, packets)) { /* Re-enable TX completion interrupts. This should * cause an immediate interrupt if any TX packets are @@ -1204,7 +1216,8 @@ static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result) * @napi: Pointer to NAPI structure. * @budget: Max number of RX packets to process. * - * Return: Number of RX packets processed. + * Return: Number of RX packets processed, or @budget to continue polling + * after a post-clear completion recheck. */ static int axienet_rx_poll(struct napi_struct *napi, int budget) { @@ -1301,6 +1314,18 @@ static int axienet_rx_poll(struct napi_struct *napi, int budget) if (tail_p) axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p); + /* Clear stale IOC/DELAY bits, flush the clear, and re-check for + * race-window completions. Skipped on budget exhaustion and on + * refill failure (cur_p->skb == NULL). + */ + if (packets < budget && cur_p->skb) { + axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, + XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); + axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); + if (cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK) + return budget; + } + if (packets < budget && napi_complete_done(napi, packets)) { if (READ_ONCE(lp->rx_dim_enabled)) { struct dim_sample sample = { -- 2.43.0