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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-161684ba3fdsm8156055c88.12.2026.10.07.11.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 11:39:06 -0700 (PDT) From: Sagar Cheluvegowda To: Maxime Chevallier , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lorenzo Bianconi , Hongmei Xu , Abhishek Chauhan , Sarosh Hasan , Sagar Cheluvegowda Subject: [PATCH net-next v2] net: stmmac: dwxgmac2: enable L2 split header support Date: Wed, 7 Oct 2026 11:39:05 -0700 Message-Id: <20261007183905.2582759-1-sagar.cheluvegowda@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: jBIhpAHKuLE82lcFvbU2w6tJ3hsbKl2e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA3NCBTYWx0ZWRfX/FFU6CBImgj2 THuazDfkg4yBUY8e6RHxCRhlvFFBRs9favvcVi5gFqmUbqHjhFvlD4T9BiUfpW+jSIA02+iGDKx z1UBOAfSsgV52iZDEQ7/I0WcHW7HvndEIVBO4CjWJ3zZQavXLUdn9MBtw6Aq5EjEIQLTVlS2zxw U/EIrgRy2TTv3E6OT3gICB3QhLruzh4gDMxOcG6PM1VRYzXf0t/8BC301uOT7azctI8EQk20Wfu smpFPugJsV9JWNqzi6bulWxW/fnVfb6WwxyAOW/Q2uLR/MjZGO+tzUgFp53f/pO9IhQsFeG6x5X YA1ANq9aS/JODg1ACMs4c1ONcxJT2j4a88ka5sdHQFaMps+uQ+8G6sFYvR1RzzdeU/Tcs5G+mVS MzNRzf8lzBCJQ2goavoz+suEeilzfUL9BqmHPWO8wNccfuoOj5Sg+AnqysgAEqntJe0SsyAq3tV UTjTu6DYjET07LdIy2g== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA3NCBTYWx0ZWRfX+kB6sLyTR4hc DoSS2/jKrAnN5W4a//sey61gRaQTX1ryO1Crq17BlBNfTxHPERjivzhUbKPcUeF6+IY+BeGy/F+ nhTdC9KUuk1Jz/viSSWUvIHHj/cGXzA= X-Proofpoint-GUID: jBIhpAHKuLE82lcFvbU2w6tJ3hsbKl2e X-Authority-Analysis: v=2.4 cv=NatzRGD4 c=1 sm=1 tr=0 ts=6ac691cc cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=4efHNOip1X5BxVcu0mkA:9 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_06,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070074 XGMAC2 doesn't program the MAC extended configuration registers needed for L2 header splitting when split-header mode is enabled, so tagged AV packets can't use the split-header path. Configure split mode (SPLM) and header saving (SAVE_EN) in XGMAC_EXT_CFG1, extending the dwmac4 sequence added by commit d10f1a4e44c3 ("net: stmmac: Programming sequence for VLAN packets with split header") to XGMAC2. Also fix the RX header-length calculation for split-header descriptors. Per the XGMAC2 descriptor format, RDES3's L34T and L2T fields are only valid on the last descriptor (LD set); on a non-last descriptor they can hold stale write-back data from a previous packet. Read the header length from RDES2[9:0] directly for non-last descriptors, and only consult L34T/L2T on the last descriptor: RDES2[9:0] for IP packets (L34T set) and RDES2[9:2] for non-IP packets (L2T set). Finally, disable the variable-length preamble when L2 splitting is enabled. A variable-length preamble shifts the position of the Ethernet header, making the L2 split offset non-deterministic. Co-developed-by: Abhishek Chauhan Signed-off-by: Abhishek Chauhan Co-developed-by: Sarosh Hasan Signed-off-by: Sarosh Hasan Signed-off-by: Sagar Cheluvegowda --- v2: - Add XGMAC_CONFIG1_SPLM_MASK and use it in XGMAC_CONFIG1_SPLM() v1: https://lore.kernel.org/netdev/20260922232116.889630-1-sagar.cheluvegowda@oss.qualcomm.com/ drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 8 ++++++++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c | 12 +++++++++++- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 ++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index f8ab347f7b5b..fb29dd489714 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -167,6 +167,12 @@ #define XGMAC_HW_FEATURE4 0x0000012c #define XGMAC_HWFEAT_EASP BIT(4) #define XGMAC_HWFEAT_PCSEL GENMASK(1, 0) +#define XGMAC_EXT_CFG0 0x140 +#define XGMAC_EXT_CFG0_VPRE BIT(8) +#define XGMAC_EXT_CFG1 0x00000144 +#define XGMAC_CONFIG1_SAVE_EN BIT(24) +#define XGMAC_CONFIG1_SPLM_MASK GENMASK(9, 8) +#define XGMAC_CONFIG1_SPLM(v) FIELD_PREP(XGMAC_CONFIG1_SPLM_MASK, v) #define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150 #define XGMAC_MAC_FSM_CONTROL 0x00000158 #define XGMAC_PRTYEN BIT(1) @@ -434,6 +440,7 @@ #define XGMAC_RDES2_L4FM BIT(28) #define XGMAC_RDES2_L3FM BIT(27) #define XGMAC_RDES2_HL GENMASK(9, 0) +#define XGMAC_RDES2_NONIPHL GENMASK(9, 2) #define XGMAC_RDES3_OWN BIT(31) #define XGMAC_RDES3_CTXT BIT(30) #define XGMAC_RDES3_IOC BIT(30) @@ -441,6 +448,7 @@ #define XGMAC_RDES3_CDA BIT(27) #define XGMAC_RDES3_RSV BIT(26) #define XGMAC_RDES3_L34T GENMASK(23, 20) +#define XGMAC_RDES3_L2T GENMASK(19, 16) #define XGMAC_RDES3_ET_LT GENMASK(19, 16) #define XGMAC_L34T_IP4TCP 0x1 #define XGMAC_L34T_IP4UDP 0x2 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c index 6719ac6e395b..65ac5403ec58 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c @@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash, static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len) { - if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T) + u32 rdes3 = le32_to_cpu(p->des3); + + /* when FD=1 and LD=0, HL is RDES2[9:0] */ + if (!(rdes3 & XGMAC_RDES3_LD)) { + *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + return; + } + + if (rdes3 & XGMAC_RDES3_L34T) *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + else if (rdes3 & XGMAC_RDES3_L2T) + *len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2; } static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index ff83858ebc1f..0a9c787305a4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr, value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ writel(value, ioaddr + XGMAC_RX_CONFIG); + value = readl(ioaddr + XGMAC_EXT_CFG1); + value |= XGMAC_CONFIG1_SPLM(1); + value |= XGMAC_CONFIG1_SAVE_EN; + writel(value, ioaddr + XGMAC_EXT_CFG1); + + /* Disable variable preambles to keep the L2 split offset deterministic. */ + value = readl(ioaddr + XGMAC_EXT_CFG0); + value &= ~XGMAC_EXT_CFG0_VPRE; + writel(value, ioaddr + XGMAC_EXT_CFG0); + value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); if (en) value |= XGMAC_SPH; -- 2.34.1