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Fri, 09 Oct 2026 13:43:33 +0000 (UTC) From: Marc Kleine-Budde To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, linux-can@vger.kernel.org, kernel@pengutronix.de, Claudiu Beznea , "Rob Herring (Arm)" , Geert Uytterhoeven , Marc Kleine-Budde Subject: [PATCH net-next 08/37] dt-bindings: can: renesas,rcar-canfd: Document RZ/G3S SoC Date: Fri, 9 Oct 2026 15:27:40 +0200 Message-ID: <20261009134323.64064-9-mkl@pengutronix.de> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261009134323.64064-1-mkl@pengutronix.de> References: <20261009134323.64064-1-mkl@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea The CAN FD controller found on the Renesas RZ/G3S SoC is largely compatible with the variant present on the RZ/G3E SoC. The main differences are: - the RZ/G3S provides only two CAN FD channels - the RZ/G3S supports only CAN FD operation; the Channel n CAN FD Configuration Register does not implement the bits used to select classical CAN-only mode (bit 30) or CAN FD-only mode (bit 28); consequently, bit 31 (CAN FD Frame Distinction Enable) of the same register is also not implemented - some bits in several registers (mainly reserved or status bits) are read-write on the RZ/G3S but read-only on the RZ/G3E; their behavior is otherwise identical: the bits read back as 0 on both SoCs and software is allowed to write only 0 to them on the RZ/G3S - the RZ/G3S provides 256 acceptance filters, compared to 768 on the RZ/G3E - the RZ/G3S can use PCLK clock as the CAN FD clock source through an internal clock divider, while also supporting an external CAN FD clock source Since: - the SoC clock generator provides to the CAN IP only the peripheral and the RAM clocks - when sourced from the peripheral clock, the CAN-FD clock is obtained inside the IP itself by dividing the peripheral clock - the assigned-clocks and assigned-clock-rates properties are specific to the CAN-FD clock the assigned-clocks and assigned-clock-rates properties were dropped from the required properties list of the Renesas RZ/G3S SoC. Add documentation for the Renesas RZ/G3S SoC. Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20260902141544.565763-2-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Marc Kleine-Budde --- .../bindings/net/can/renesas,rcar-canfd.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml index b9d9dd7a7967..bbaaef8f4282 100644 --- a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - renesas,r9a08g045-canfd # RZ/G3S - renesas,r9a09g047-canfd # RZ/G3E - renesas,r9a09g077-canfd # RZ/T2H @@ -185,8 +186,6 @@ required: - clocks - clock-names - power-domains - - assigned-clocks - - assigned-clock-rates - channel0 - channel1 @@ -198,6 +197,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,rzg2l-canfd then: properties: @@ -266,6 +266,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,r9a09g077-canfd - renesas,rcar-gen3-canfd - renesas,rzg2l-canfd @@ -330,6 +331,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,r9a09g047-canfd - renesas,rzg2l-canfd then: @@ -350,6 +352,20 @@ allOf: properties: reset-names: false + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-canfd + then: + properties: + renesas,no-can-fd: false + renesas,fd-only: false + else: + required: + - assigned-clocks + - assigned-clock-rates + unevaluatedProperties: false examples: -- 2.53.0