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Miller" , Andrew Lunn , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "imx@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" Subject: Re: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz Message-ID: <20261013152559.cnh2i7i36hak6z3t@skbuf> References: <20260924180607.60932-1-marex@nabladev.com> Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-ClientProxiedBy: WA2P291CA0020.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1e::9) To AM0PR04MB6900.eurprd04.prod.outlook.com (2603:10a6:208:17d::10) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR04MB6900:EE_|GVXPR04MB10204:EE_ X-MS-Office365-Filtering-Correlation-Id: e0602c8a-4d84-4a04-f4cd-08df293e4ac8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|23010399003|1800799024|10070799003|376014|366016|22082099003|18002099003|10067099003|4143699003|261009223027099003|11063799006|56012099006; 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Yes. On LS1028A, the ENETC clock selection is made by a mux called HWA_CGA_M4_CLK_SEL (Hardware Accelerator Block Cluster Group A Mux 4 Clock Select). You can describe that in ls1028a.dtsi like this (note that in the RM, the mux numbering is one-based, while in the device tree it is 0-based, so 3 is actually "MUX 4"): enetc_mdio_pf3: mdio@0,3 { compatible = "pci1957,ee01", "fsl,enetc-mdio"; reg = <0x000300 0 0 0 0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; #address-cells = <1>; #size-cells = <0>; }; Upon clk_get_rate(), the qoriq clockgen driver will use the device tree definition to index the hwaccel[] array and find the ls1028a_hwa4 structure. This defines what values the HWA4CSR register can legally take, and what each means. It will read HWA4CSR[HWACLKSEL] as 0011 (meaning Cluster PLL2 divide-by-3). Then to calculate this clock rate, it knows it must read CGA_PLL2 and to divide by PLL_DIV3 (1200 / 3 = 400 MHz). Note the ENETC PTP device already has this property defined (which is OK, all ENETC devices share the same clock). Without a 'clocks' and/or 'clock-frequency' property, we have to figure out a default that works for everyone, or if that fails. For example, with 400 MHz enet_clk on LS1028A, the original MDIO_CFG_CLKDIV value of 258 used to produce an MDC frequency of 400000000÷((258×2)+1)=773 KHz. Your new MDIO_CFG_CLKDIV value of 66 produces 400000000÷((66)+1)=3 MHz, which is too high to be a default value. So from LS perspective, this patch needs to be reverted. Generally it is assumed that low MDIO clock frequencies are not a problem. Otherwise, drivers/net/mdio/mdio-bitbang.c could never work. It seems TJA1120 is the odd one for requiring a maximum MDC clock period of 1000 ns. Please use xgmac_mdio_set_mdc_freq() as model, since it exists to solve a very similar issue as you are trying to do.