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This series adds a DPLL subsystem driver for the SiTime SiT95316 and=0A= SiT95317 I2C clock generators. Each device integrates four PLLs with=0A= automatic reference selection and on-chip TDC phase-offset measurement,=0A= and is used for synchronization in telecom, networking, and data-center=0A= timing.=0A= =0A= What is here is the device-tree binding, the driver under=0A= drivers/dpll/sit9531x/, and the MAINTAINERS entry. Patch 1 of v11 was=0A= applied to net-next as commit 45ad84d2800e ("dt-bindings: dpll: allow=0A= hex unit addresses on output pins"), which is why the count is twelve=0A= and not thirteen.=0A= =0A= v1: https://lore.kernel.org/netdev/20260511211143.19792-1-arouhi@sitime.com= /=0A= v2: https://lore.kernel.org/netdev/20260520191943.73938-1-arouhi@sitime.com= /=0A= v3: https://lore.kernel.org/netdev/20260731180951.65725-1-arouhi@sitime.com= /=0A= v4: https://lore.kernel.org/netdev/20260806232439.27551-1-arouhi@sitime.com= /=0A= v5: https://lore.kernel.org/netdev/20260810230439.22866-1-arouhi@sitime.com= /=0A= v6: https://lore.kernel.org/netdev/20260812175337.18155-1-arouhi@sitime.com= /=0A= v7: https://lore.kernel.org/netdev/20260815221919.64226-1-arouhi@sitime.com= /=0A= v8: https://lore.kernel.org/netdev/20260902214030.20955-1-arouhi@sitime.com= /=0A= v9: https://lore.kernel.org/netdev/20260915000015.80480-1-arouhi@sitime.com= /=0A= v10: https://lore.kernel.org/netdev/20260921201108.42676-1-arouhi@sitime.co= m/=0A= v11: https://lore.kernel.org/netdev/20260930233714.87679-1-arouhi@sitime.co= m/=0A= v12: https://lore.kernel.org/netdev/20261009183151.78497-1-arouhi@sitime.co= m/=0A= =0A= Ivan Vecera reviewed v12. He gave his Reviewed-by on six patches and=0A= left comments on four; patch 9 has both. All four comments are=0A= addressed here, folded into the patch that introduces the code rather=0A= than added as a follow-up, so each patch still reads as the one change=0A= it describes. The replies go out with this series. There is no code=0A= change in v13 beyond those four, one locking change described below,=0A= and the line wrapping and kernel-doc items the patchwork checks=0A= reported.=0A= =0A= His Reviewed-by is carried on patches 4, 6, 7, 9 and 11. Patches 4=0A= and 7 are unchanged from v12. Patch 9 carries the reordering he asked=0A= for, patch 11 a kernel-doc Return line, and patch 6 the line wrapping=0A= noted below. It is not carried on patch 5. That patch now takes=0A= multiop_lock around the probe-time output state fetch, which he has=0A= not seen; the three functions it makes static are the change he asked=0A= for in patch 3.=0A= =0A= 1 bindings: vendor prefix=0A= 2 bindings: the device schema=0A= 3 basic support: paged regmap, variant detection, probe=0A= 4 DPLL types and pin properties from system firmware=0A= 5 register the DPLL devices and pins, and keep their state=0A= 6 input pin state and operational state on a DPLL=0A= 7 input pin priority=0A= 8 pin frequency, both directions=0A= 9 output pin state (mute)=0A= 10 output phase adjust=0A= 11 phase offset through the TDC=0A= 12 the inter-PLL sync net as a pair of pins=0A= =0A= The two bindings patches come first, so the driver never matches on a=0A= compatible string before the schema that describes it is in the tree.=0A= =0A= Each of the ten driver patches builds and links on its own: no patch=0A= calls something a later patch introduces, so a bisect cannot land on a=0A= tree that fails to compile. That was re-checked for this posting patch=0A= by patch with W=3D1 and with sparse, and kernel-doc -Wall is clean on=0A= every patch. checkpatch --strict at 80 columns is clean except for the=0A= "does MAINTAINERS need updating?" hint on patches 4 and 5, which add=0A= files under drivers/dpll/sit9531x/ -- patch 3 already covers that=0A= directory with an F: entry.=0A= =0A= One change in this series did not come from the thread. A review of=0A= v12 by the netdev AI reviewer, which reached us off-list, asked why=0A= sit9531x_out_state_fetch() runs without multiop_lock at probe when=0A= every other caller of a paged-register sequence holds it. Nothing runs=0A= concurrently before registration, so there was no bug, but the fetch=0A= walks the same paged registers under the same contract and now holds=0A= the lock the same way. That is the seven-line change in patch 5.=0A= =0A= Changes in v13:=0A= =0A= - Patch 3: sit9531x_regmap_config and sit9531x_dev_probe() are=0A= static and their declarations are gone from core.h.=0A= =0A= - Patch 5: sit9531x_dev_start(), sit9531x_dev_stop() and=0A= sit9531x_clear_notifications() are static, the same change, and=0A= only core.c calls them. The probe-time output state fetch runs=0A= under multiop_lock.=0A= =0A= - Patch 8: the output rate read-back sat before the=0A= skip_fwnode_props label, so an output the board describes without=0A= a rate list, or does not describe at all, kept a cached rate of=0A= zero and published only the 1 Hz to 1 GHz fallback range. The=0A= read-back was meant for every output; it now sits past the label,=0A= so each output publishes the rate its divider produces ahead of=0A= the fallback range.=0A= =0A= - Patch 10: a zero phase request returns with coarse, fine and the=0A= adjustment set to zero, before the divisions.=0A= =0A= - Patch 9: local declarations in reverse xmas tree order, and the=0A= same ordering applied across the driver wherever the swap was=0A= free. Blocks whose order carries a dependency are unchanged.=0A= =0A= - Patch 11: a Return line in the sit9531x_input_mon_fetch=0A= kernel-doc.=0A= =0A= - Lines over 80 columns wrapped in patches 6, 8 and 10. The one in=0A= patch 6 takes a local const u8 *prev for the two prio_srcs reads=0A= in the rollback loop; the rest are re-indentation.=0A= =0A= - Reviewed-by from Ivan Vecera carried on patches 4, 6, 7, 9 and 11.=0A= =0A= Ali Rouhi (2):=0A= dt-bindings: vendor-prefixes: add SiTime Corporation=0A= dt-bindings: dpll: add SiTime SiT95316 clock generator=0A= =0A= Oleg Zadorozhnyi (10):=0A= dpll: add basic SiTime SiT9531x support=0A= dpll: sit9531x: read DPLL types and pin properties from system=0A= firmware=0A= dpll: sit9531x: register DPLL devices and pins=0A= dpll: sit9531x: implement input pin state on a DPLL=0A= dpll: sit9531x: add support to get and set priority on input pins=0A= dpll: sit9531x: add support to get and set frequency on pins=0A= dpll: sit9531x: implement output pin state on a DPLL=0A= dpll: sit9531x: add support to adjust output phase=0A= dpll: sit9531x: add support to get phase offset on the connected input=0A= pin=0A= dpll: sit9531x: model the inter-PLL sync net as a pair of pins=0A= =0A= .../bindings/dpll/sitime,sit95316.yaml | 213 +=0A= .../devicetree/bindings/vendor-prefixes.yaml | 2 +=0A= MAINTAINERS | 7 +=0A= drivers/dpll/Kconfig | 2 +=0A= drivers/dpll/Makefile | 1 +=0A= drivers/dpll/sit9531x/Kconfig | 17 +=0A= drivers/dpll/sit9531x/Makefile | 4 +=0A= drivers/dpll/sit9531x/core.c | 5320 +++++++++++++++++=0A= drivers/dpll/sit9531x/core.h | 443 ++=0A= drivers/dpll/sit9531x/dpll.c | 1731 ++++++=0A= drivers/dpll/sit9531x/dpll.h | 70 +=0A= drivers/dpll/sit9531x/prop.c | 476 ++=0A= drivers/dpll/sit9531x/prop.h | 37 +=0A= drivers/dpll/sit9531x/regs.h | 425 ++=0A= 14 files changed, 8748 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= create mode 100644 drivers/dpll/sit9531x/Kconfig=0A= create mode 100644 drivers/dpll/sit9531x/Makefile=0A= create mode 100644 drivers/dpll/sit9531x/core.c=0A= create mode 100644 drivers/dpll/sit9531x/core.h=0A= create mode 100644 drivers/dpll/sit9531x/dpll.c=0A= create mode 100644 drivers/dpll/sit9531x/dpll.h=0A= create mode 100644 drivers/dpll/sit9531x/prop.c=0A= create mode 100644 drivers/dpll/sit9531x/prop.h=0A= create mode 100644 drivers/dpll/sit9531x/regs.h=0A= =0A= =0A= base-commit: 45ad84d2800e4a092fb8d96006a533b2d0ab13f6=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=