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[95.235.252.189]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a1b35d64e4sm18756285e9.0.2026.10.14.00.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:17:54 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , Ahmed Naseef , Joris Vaisvila , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v3 0/6] net: phy: mediatek: calibration for AN7581/3 Date: Wed, 14 Oct 2026 09:17:31 +0200 Message-ID: <20261014071739.216345-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This small series adds calibration support for Airoha AN7581 and AN7583 integrated PHYs. The calibration logic is quite big so I decided to split the driver from the mediatek one to keep things organized. Minor change were needed and just additional symbol to use what is common between mediatek and airoha PHYs. I followed the naming pattern of mtk by calling the new source airoha-ge-soc and related config. The calibration use lots of static table and software calibration at runtime instead of using efuse to calibrate. There is one pecularity where some register and calibration needs to be done on port0 first and then with the related port. This is O.K. as port0 presence is mandatory for the functionality of the integrated switch and it's assumed to be always present on the MDIO bus. MAINTAINERS is updated to reflect the changed code. (this was tested from a long time and also verified by Airoha for correct order of calibration) Changes v3: - Address comments from sashiko bot - Apply review and suggested changes from Airoha - Rebase on top of net-next Changes v2: - Split header register patch from cal_cycle part - Fix missing EXPORT_SYMBOL_GPL Christian Marangi (6): net: phy: mediatek: export __mtk_tr_write net: phy: mediatek: move MTK GE SoC registers define to dedicated header net: phy: mediatek: generalize cal_cycle function for GE SoC net: phy: mediatek: split Airoha code to dedicated source net: phy: mediatek: add calibration logic for AN7581 net: phy: mediatek: add calibration logic for AN7583 MAINTAINERS | 9 + drivers/net/phy/mediatek/Kconfig | 18 +- drivers/net/phy/mediatek/Makefile | 1 + drivers/net/phy/mediatek/airoha-ge-soc.c | 1851 ++++++++++++++++++++++ drivers/net/phy/mediatek/mtk-ge-soc.c | 553 +------ drivers/net/phy/mediatek/mtk-ge-soc.h | 377 +++++ drivers/net/phy/mediatek/mtk-phy-lib.c | 77 +- drivers/net/phy/mediatek/mtk.h | 15 + 8 files changed, 2365 insertions(+), 536 deletions(-) create mode 100644 drivers/net/phy/mediatek/airoha-ge-soc.c create mode 100644 drivers/net/phy/mediatek/mtk-ge-soc.h -- 2.55.0