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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Dragos Tatulea , Gal Pressman , "Joe Damato" , Leon Romanovsky , open list , , Mark Bloch , "Nabil S. Alramli" , Rahul Rameshbabu , Saeed Mahameed , Tariq Toukan , Yael Chemla Subject: [PATCH net 1/3] net/mlx5e: Sync CQE moderation pflags with coalesce params Date: Wed, 14 Oct 2026 15:47:02 +0300 Message-ID: <20261014124704.1017782-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261014124704.1017782-1-tariqt@nvidia.com> References: <20261014124704.1017782-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F7:EE_|SJ0PR12MB7081:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c305480-2ddd-4b4f-1f34-08df29f16789 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|23010399003|376014|82310400026|7416014|261009223027099003|56012099006|11063799006|22082099003|10067099003|6133799003|18002099003; X-Microsoft-Antispam-Message-Info: 6JsOtGAzUJGiSrxt1whtcqz9nixkAFPA5cCN6yRKEbUpjw53raxfadSJF+9LcTeyoSEfBDUoWlfeFemys9F6pooV51hRgZHs3hx+d33MJ59oIweG9uSAZ4oi4mzkgQA3s5vGCTRayStMV3O4mDPqW2rW14LwS+RyVgEknG3CyR09f95CTTB78fcPVj3LsP8d8kJ7BX0JCzCVDCnmVCWmEOV1C6zgFKN1ZBy4Z6AkpoGD0zrhUO517a5GCpJGSF0KkCbjt1O9YJvQ7yCnq/evx4BvlZx1DkPgT59kt01Uj35PfBFT55YdnZfnU1ZylhcBbzYoa4kB2eJF2TlWrxUUTXSsGfTdouxZzeUFUOCx2cbbs9yaFxJ4xGKFJ64/fq6SC4KubfM7yL4Ayjtybb5fNreQmlAHpBuip32GpcRAtayTbGQhF2klRklSAjzTaNWXOq6BwQTn28vnw7d1SADIzPl+nQJMvknlpqo4s6OJ21ZraSCJv69jdRYAfkQ5L7vFfShy+CkoIouMM6nkGyodrMmkCq8oKybijvD5dacAKcdC6IcyDBcosoVcTLYTyXY58Q7sBcsbfAwPFgw8/Czb+k2x5hhHJsRQMHN9tfAFf8tUP3NNAcLOxK0TbCgZNeRZ+CuNdKNcRbnHSAnk6/aO2escPOYVM9jKdE/scI3/+tTXknxk9B/2kF/Gk/rCax0dd08Y6MBz365kVHK15C6vIQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(23010399003)(376014)(82310400026)(7416014)(261009223027099003)(56012099006)(11063799006)(22082099003)(10067099003)(6133799003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DU3FRHqvr9eNAvLgCRUR60nq+c0ww/6Sn2HKdbneSc2GKvEedfjBx6J5404MODUQ5V+0PHTQqbPt4XkfWAg9d70I3YHZwxzRfTA2dqjBXJOHn8Cx+pUjSJ1/Pt9EysGX0owaySjtbWXae9dKOIlBDDCcuyoxwiUecodmcU26HyCHJLxYdtmaAzOGb2tRmimG/MN9C9DlX+IBKkqSk3pkzYriBLuywp2PNQ+JsYE2Xl7xfOkXI3XuaesDci80tukB+rmNkyfS7cIUcfQe2EgPVrK+JRDclgxzDX/7Um2F9S6oZ9Q3MOp/2JMqU0YlVEkemENibPs3By9b4vsG0lGnIDIQxGAtqRhm7T5O2zFCzxRWiYppUUff96bFVE1cyVccE5fgTZd3KdHmoySWJInlkGVAllhOeohc7ylDbR6cyphG394/NoZ47EOtKFwaOnIk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2026 12:48:11.0645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c305480-2ddd-4b4f-1f34-08df29f16789 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7081 From: Yael Chemla mlx5e_params keeps two representations of CQE moderation: the private flags (MLX5E_PFLAG_RX_CQE_BASED_MODER, MLX5E_PFLAG_TX_CQE_BASED_MODER) and the fields rx_moder_use_cqe_mode / tx_moder_use_cqe_mode, which are used by ethtool get/set coalesce. Both are used by the driver (ethtool get/set coalesce, channel open, moderation apply). When they disagree, CQE moderation reported value is wrong. Such an issue can be seen on channel attach or reopen: mlx5e_build_nic_params() runs and sets rx_moder_use_cqe_mode and tx_moder_use_cqe_mode from device capability but did not set the corresponding pflags. So after attach/reopen, pflags could remain zero while the fields reflected hardware configuration. Fix by syncing pflags in build_nic_params from the capability-derived fields. Reproducer: ethtool --show-priv-flags eth2 | grep rx_cqe_moder rx_cqe_moder : off ethtool --coalesce eth2 adaptive-tx off ethtool --show-priv-flags eth2 | grep rx_cqe_moder rx_cqe_moder : on Fixes: 445a25f6e1a2 ("net/mlx5e: Support updating coalescing configuration without resetting channels") Signed-off-by: Yael Chemla Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 4c6060d54fbe..9fcea0395137 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5407,6 +5407,10 @@ void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 MLX5_CAP_GEN(mdev, cq_period_mode_modify); params->rx_moder_use_cqe_mode = !!MLX5_CAP_GEN(mdev, cq_period_start_from_cqe); params->tx_moder_use_cqe_mode = false; + MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, + params->rx_moder_use_cqe_mode); + MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, + params->tx_moder_use_cqe_mode); mlx5e_reset_rx_moderation(¶ms->rx_cq_moderation, params->rx_moder_use_cqe_mode, params->rx_dim_enabled); mlx5e_reset_tx_moderation(¶ms->tx_cq_moderation, params->tx_moder_use_cqe_mode, -- 2.44.0