[PATCH net-next v14 00/12] dpll: add SiTime SiT9531x DPLL clock driver

[Ali Rouhi <arouhi@sitime.com>]

This series adds a DPLL subsystem driver for the SiTime SiT95316 and
SiT95317 I2C clock generators. Each device integrates four PLLs with
automatic reference selection and on-chip TDC phase-offset measurement,
and is used for synchronization in telecom, networking, and data-center
timing.

What is here is the device-tree binding, the driver under
drivers/dpll/sit9531x/, and the MAINTAINERS entry. Patch 1 of v11 was
applied to net-next as commit 45ad84d2800e ("dt-bindings: dpll: allow
hex unit addresses on output pins"), which is why the count is twelve
and not thirteen.

v1: https://lore.kernel.org/netdev/20260511211143.19792-1-arouhi@sitime.com/
v2: https://lore.kernel.org/netdev/20260520191943.73938-1-arouhi@sitime.com/
v3: https://lore.kernel.org/netdev/20260731180951.65725-1-arouhi@sitime.com/
v4: https://lore.kernel.org/netdev/20260806232439.27551-1-arouhi@sitime.com/
v5: https://lore.kernel.org/netdev/20260810230439.22866-1-arouhi@sitime.com/
v6: https://lore.kernel.org/netdev/20260812175337.18155-1-arouhi@sitime.com/
v7: https://lore.kernel.org/netdev/20260815221919.64226-1-arouhi@sitime.com/
v8: https://lore.kernel.org/netdev/20260902214030.20955-1-arouhi@sitime.com/
v9: https://lore.kernel.org/netdev/20260915000015.80480-1-arouhi@sitime.com/
v10: https://lore.kernel.org/netdev/20260921201108.42676-1-arouhi@sitime.com/
v11: https://lore.kernel.org/netdev/20260930233714.87679-1-arouhi@sitime.com/
v12: https://lore.kernel.org/netdev/20261009183151.78497-1-arouhi@sitime.com/
v13: https://lore.kernel.org/netdev/20261013224131.27149-1-arouhi@sitime.com/

Rob Herring pointed out on patch 2 that a -hz property is 32-bit. The
binding described the input rate list as 64-bit and the examples wrote
/bits/ 64; the driver read the lists with the u64 property helpers to
match. Both are now 32-bit, and the input list takes the maxItems: 1
that its description had always stated in words. No rate of this part
needs more than 32 bits.

The netdev AI reviewer looked at v13 and raised eight points across
five patches. Four are real and are fixed here, each folded into the
patch that introduces the code rather than added as a follow-up, so
every patch still reads as the one change it describes. The other four
do not hold as written, and the replies going out with this series say
why for each.

  1     bindings: vendor prefix
  2     bindings: the device schema
  3     basic support: paged regmap, variant detection, probe
  4     DPLL types and pin properties from system firmware
  5     register the DPLL devices and pins, and keep their state
  6     input pin state and operational state on a DPLL
  7     input pin priority
  8     pin frequency, both directions
  9     output pin state (mute)
  10    output phase adjust
  11    phase offset through the TDC
  12    the inter-PLL sync net as a pair of pins

The two bindings patches come first, so the driver never matches on a
compatible string before the schema that describes it is in the tree.

Each of the ten driver patches builds and links on its own: no patch
calls something a later patch introduces, so no step of a bisect
reaches a tree that fails to compile. That was re-checked for this posting patch
by patch with W=1 and with sparse, and kernel-doc -Wall is clean on
every patch. checkpatch --strict at 80 columns is clean except for the
"does MAINTAINERS need updating?" hint on patches 4 and 5, which add
files under drivers/dpll/sit9531x/ -- patch 3 already covers that
directory with an F: entry.

Changes in v14:

  - Patch 2: supported-frequencies-hz on an input takes maxItems: 1,
    and the examples drop /bits/ 64 from every -hz value.

  - Patch 4: the frequency lists are read with the u32 property
    helpers. The crystal rate is no longer written into the input it
    describes ahead of the allocation that can still fail; every
    input publishes its rate at the same point, once the allocation
    has succeeded.

  - Patch 5: the probe-time channel state fetch runs under
    multiop_lock, alongside the output fetch that already did. It
    walks the priority table, which every other caller reads with the
    lock held. The lock itself is not new -- it arrived one patch
    later in v12 and v13, which is where reading patch 5 on its own
    showed the gap.

  - Patch 10: two error paths in the output rate set recorded the
    phase as stale but not the realignment the output still needed.
    Both now record it. The one that had already committed a re-timed
    delay now caches the value it committed rather than marking it
    stale, because a stale mark makes the getter publish the
    committed value anyway, the core then drops an identical retry,
    and the realignment never runs.

  - Patch 12: a resume that cannot read the INTSYNC source back marks
    the cached value stale instead of leaving the pre-suspend value in
    place. The five pin callbacks that report or change that state
    read the source from the device first, and fail with an extack
    message if the read still does not work.

  - Reviewed-by from Ivan Vecera carried on patches 4, 6, 7, 9 and 11.
    Patches 7, 9 and 11 are unchanged from v13. Patch 4 carries the
    u32 change above and patch 6 one widened comment.

Ali Rouhi (2):
  dt-bindings: vendor-prefixes: add SiTime Corporation
  dt-bindings: dpll: add SiTime SiT95316 clock generator

Oleg Zadorozhnyi (10):
  dpll: add basic SiTime SiT9531x support
  dpll: sit9531x: read DPLL types and pin properties from system
    firmware
  dpll: sit9531x: register DPLL devices and pins
  dpll: sit9531x: implement input pin state on a DPLL
  dpll: sit9531x: add support to get and set priority on input pins
  dpll: sit9531x: add support to get and set frequency on pins
  dpll: sit9531x: implement output pin state on a DPLL
  dpll: sit9531x: add support to adjust output phase
  dpll: sit9531x: add support to get phase offset on the connected input
    pin
  dpll: sit9531x: model the inter-PLL sync net as a pair of pins

 .../bindings/dpll/sitime,sit95316.yaml        |  214 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    2 +
 MAINTAINERS                                   |    7 +
 drivers/dpll/Kconfig                          |    2 +
 drivers/dpll/Makefile                         |    1 +
 drivers/dpll/sit9531x/Kconfig                 |   17 +
 drivers/dpll/sit9531x/Makefile                |    4 +
 drivers/dpll/sit9531x/core.c                  | 5333 +++++++++++++++++
 drivers/dpll/sit9531x/core.h                  |  446 ++
 drivers/dpll/sit9531x/dpll.c                  | 1783 ++++++
 drivers/dpll/sit9531x/dpll.h                  |   70 +
 drivers/dpll/sit9531x/prop.c                  |  476 ++
 drivers/dpll/sit9531x/prop.h                  |   37 +
 drivers/dpll/sit9531x/regs.h                  |  425 ++
 14 files changed, 8817 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml
 create mode 100644 drivers/dpll/sit9531x/Kconfig
 create mode 100644 drivers/dpll/sit9531x/Makefile
 create mode 100644 drivers/dpll/sit9531x/core.c
 create mode 100644 drivers/dpll/sit9531x/core.h
 create mode 100644 drivers/dpll/sit9531x/dpll.c
 create mode 100644 drivers/dpll/sit9531x/dpll.h
 create mode 100644 drivers/dpll/sit9531x/prop.c
 create mode 100644 drivers/dpll/sit9531x/prop.h
 create mode 100644 drivers/dpll/sit9531x/regs.h


base-commit: 45ad84d2800e4a092fb8d96006a533b2d0ab13f6
-- 
2.39.2 (Apple Git-143)