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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a211be8f79sm11958795e9.14.2026.10.22.15.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 15:30:20 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 4/4] net: phy: as21xxx: handle odd firmware on loading Date: Fri, 23 Oct 2026 00:29:54 +0200 Message-ID: <20261022222955.698722-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261022222955.698722-1-ansuelsmth@gmail.com> References: <20261022222955.698722-1-ansuelsmth@gmail.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Even if firmware for AS21xxx should be always u16 aligned, we can't assume this will be the same forever. Better address this by simply validate the index before reading out of bound from the data buffer. A zero padded buffer will be passed to the AS21xxx mailbox in such case. Fixes: 830877d89edc ("net: phy: Add support for Aeonsemi AS21xxx PHYs") Signed-off-by: Christian Marangi --- Changes v2: - Add this patch drivers/net/phy/as21xxx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/as21xxx.c b/drivers/net/phy/as21xxx.c index e2988cb10c04..db1a7cd68cef 100644 --- a/drivers/net/phy/as21xxx.c +++ b/drivers/net/phy/as21xxx.c @@ -325,7 +325,9 @@ static int aeon_firmware_boot(struct phy_device *phydev, const u8 *data, /* Firmware is always aligned to u16 */ for (i = 0; i < size; i += 2) { - val = data[i + 1] << 8 | data[i]; + val = data[i]; + if (i + 1 < size) + val |= data[i + 1] << 8; ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_MDIO_INDIRECT_LOAD, val); -- 2.55.0