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[153.223.97.46]) by smtp.googlemail.com with ESMTPSA id 5a478bee46e88-369e8ec50bcsm23813952eec.23.2026.10.24.19.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 19:45:20 -0700 (PDT) From: Daniel Palmer To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Daniel Palmer , Denis Ahrens Subject: [PATCH] net: i825xx: 82596: use MMIO accessors for the MVME16x PORT/CA registers Date: Sun, 25 Oct 2026 11:45:14 +0900 Message-ID: <20261025024514.802862-1-daniel@0x0f.com> X-Mailer: git-send-email 2.55.0 X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On the MVME16x the two port registers need to be written in order to latch the correct 32bit value. The way the code is currently written means that modern GCC can decide to optimize the writes and break that latching. Convert the MVME16x specific register accesses to use the proper io accessors to restore the latching and make the driver functional again. Reported-by: Denis Ahrens Signed-off-by: Daniel Palmer --- Denis emailed me with his fix for this issue which added volatile to the struct members to stop the compiler getting too clever. This is my version of the fix. Dennis, please test it actually works :). Also, this driver is old and does need to be converted over to being a platform driver etc. I have a set of patches to do this. I'd like to just fix the driver first so it works again so the conversion to a platform driver is working against a working driver. drivers/net/ethernet/i825xx/82596.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/i825xx/82596.c b/drivers/net/ethernet/i825xx/82596.c index 773d7aa29ef5..bb8798b0d3ae 100644 --- a/drivers/net/ethernet/i825xx/82596.c +++ b/drivers/net/ethernet/i825xx/82596.c @@ -196,11 +196,10 @@ enum commands { #define TX_TIMEOUT (HZ/20) -struct i596_reg { - unsigned short porthi; - unsigned short portlo; - unsigned long ca; -}; +/* MVME16x: the 82596 PORT and CA registers */ +#define MVME_I596_PORT_HI 0x00 +#define MVME_I596_PORT_LO 0x02 +#define MVME_I596_CA 0x04 #define EOF 0x8000 #define SIZE_MASK 0x3fff @@ -375,7 +374,9 @@ static inline void CA(struct net_device *dev) { #ifdef ENABLE_MVME16x_NET if (MACH_IS_MVME16x) { - ((struct i596_reg *) dev->base_addr)->ca = 1; + void __iomem *regs = (void __iomem *)dev->base_addr; + + __raw_writel(1, regs + MVME_I596_CA); } #endif #ifdef ENABLE_BVME6000_NET @@ -392,9 +393,15 @@ static inline void MPU_PORT(struct net_device *dev, int c, volatile void *x) { #ifdef ENABLE_MVME16x_NET if (MACH_IS_MVME16x) { - struct i596_reg *p = (struct i596_reg *) (dev->base_addr); - p->porthi = ((c) | (u32) (x)) & 0xffff; - p->portlo = ((c) | (u32) (x)) >> 16; + void __iomem *regs = (void __iomem *)dev->base_addr; + u32 v = (u32)c | (u32)x; + + /* + * The 32bit value is latched on the write of the lo register, + * so the 16bit writes must happen in this order. + */ + __raw_writew(v & 0xffff, regs + MVME_I596_PORT_HI); + __raw_writew(v >> 16, regs + MVME_I596_PORT_LO); } #endif #ifdef ENABLE_BVME6000_NET -- 2.55.0