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Tue, 27 Oct 2026 08:02:24 -0700 From: Chris Babroski To: CC: , , , , , , , , , , , , , , , Subject: RE: [PATCH net-next v1 1/5] net: lan743x: reset DMA channels that fail to stop Date: Tue, 27 Oct 2026 11:02:14 -0400 Message-ID: <20261027150214.565776-1-cbabroski@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PEPF000000A2:EE_|CH8PR12MB9839:EE_ X-MS-Office365-Filtering-Correlation-Id: fb85af38-4231-4bd4-750f-08df343b65c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|23010399003|82310400026|261026140227099003|11063799006|56012099006|261009223027099003|261021135927099003|261022075727099003|10067099003|261022105027099003|22082099003|18002099003|261026121527099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 642WUIpMtXuMKFI6cGIeTRj0n5I5IUc9gsztNqMawvWvHvSJLlI0zks8HvJ8YtFEJH7fWWh/w6Rfz3cUY4rf6InNeXvLtEjq6XCCoj3O/6Ut2taZPJIdLHN8FFJX20YWckCUnag4rNj1cYekg+ot9m7hiilDCDri43XVG6LyKFXxzAkDjtiMfy/QnyXLvNwejlXfEwchUnXpQkICXBLM3eUVAjzTvdSPEsb5NB5lryWEqUlpDygoFQtYy7T9EE3uQz/q0dcSsExyJVipc6/7kSci2Yla2W7SCaW/6QOELGHLAEJHlmibJfObaL93AlchOyfWg24NcrMzxPz7Wy7gm1vETION3He4N/ZWt9C5XgcvfbEKkgsDyo896WxdxizD84IGlkPJs7TK7yMJBJOGGlmqimN+9feRVdVDuN6aRuDIpffVI76T0F4IIkFi0B3O X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2026 15:03:02.3315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb85af38-4231-4bd4-750f-08df343b65c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF000000A2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9839 Hi Woojung and Nicolai, > Recommended way of setting TX_SWR_x is after stopping and flushing FCT > to avoid in-flight frames during TX DMA reset. > > lan743x_dmac_tx_reset() is already called lan743x_tx_open() with > proper sequence of initializing FCT at lan743x_netdev_open(). > > lan743x_reset_work() in the patch 4/5 is doing lan743x_netdev_close(), > ... and lan743x_netdev_open(), I think no additional > lan743x_dmac_tx_reset() may be needed at failure of > lan743x_dmac_tx_wait_till_stopped() in lan743x_tx_close(). > > Hi Chris, > Did you see calling lan743x_dmac_tx_reset() at lan743x_tx_close() is a > necessary step in addition to lan743x_dmac_tx_reset() at > lan743x_tx_open() when lockup happened? Thanks for clarifying the reset flow. I did not see that it is unnecessary, but is it an issue to leave the DMAC in a started state on close if the descriptor ring was freed even though the FIFO is disabled after? I can remove the call to lan743x_dmac_tx_reset() in lan743x_tx_close(). It sounds like changing the order of lan743x_tx_close() to disable FIFO beforehand could also work, but that feels out of scope for this patch series. I also noticed in lan743x_rx_close() the FIFO is already disabled before checking DMAC channel state. This means we can leave the call to lan743x_dmac_rx_reset() inside lan743x_rx_close() or I can remove it as well if you prefer. Thanks, Chris